A simple CPU, FPGA implementation to streamline the instruction set architecture, each instruction 16bit, high three operands for the instruction, the 13 address, the CPU can achieve the eight kinds of instruction operations, respectively, HLT (a medium-term empty) ADD (add operation) SKZ (zero skip) AND (phase operation) the XOR (exclusive OR operation) LDA (read data) STO (write data) JMP (unconditional jump instruction). cpu consists of eight parts, clock generator, the instruction register, accumulator, arithmetic logic unit, the data controller, the state controller, the program counter, the address multiplexer, the various components interoperate relations by the state controller to control, program instructions stored in the initial rom the routines stored in memory the initial file. PS: Why is there no Verilog options.

RISC CPU\accum.v
........\addr_decode.v
........\adr.v
........\altera_mf.v
........\alu.v
........\clk_gen.v
........\counter.v
........\CPU.asm.rpt
........\CPU.done
........\CPU.fit.rpt
........\CPU.fit.smsg
........\CPU.fit.summary
........\CPU.flow.rpt
........\CPU.map.rpt
........\CPU.map.smsg
........\CPU.map.summary
........\CPU.pin
........\CPU.pof
........\CPU.qpf
........\CPU.qsf
........\CPU.qws
........\CPU.sof
........\CPU.tan.rpt
........\CPU.vwf
........\cpu_ram_1.hex
........\cpu_ram_1.v
........\cpu_ram_1.ver
........\cpu_rom_1.hex
........\cpu_rom_1.v
........\cpu_rom_1.ver
........\cpu_top.v
........\cpu_tp.v
........\datactl.v
........\.b\altsyncram_98d1.tdf
........\..\altsyncram_s581.tdf
........\..\CPU.asm.qmsg
........\..\CPU.asm_labs.ddb
........\..\CPU.cbx.xml
........\..\CPU.cmp.bpm
........\..\CPU.cmp.cdb
........\..\CPU.cmp.ecobp
........\..\CPU.cmp.hdb
........\..\CPU.cmp.kpt
........\..\CPU.cmp.logdb
........\..\CPU.cmp.rdb
........\..\CPU.cmp.tdb
........\..\CPU.cmp0.ddb
........\..\CPU.cmp2.ddb
........\..\CPU.cmp_merge.kpt
........\..\CPU.db_info
........\..\CPU.eco.cdb
........\..\CPU.fit.qmsg
........\..\CPU.hier_info
........\..\CPU.hif
........\..\CPU.lpc.html
........\..\CPU.lpc.rdb
........\..\CPU.lpc.txt
........\..\CPU.map.bpm
........\..\CPU.map.cdb
........\..\CPU.map.ecobp
........\..\CPU.map.hdb
........\..\CPU.map.kpt
........\..\CPU.map.logdb
........\..\CPU.map.qmsg
........\..\CPU.map_bb.cdb
........\..\CPU.map_bb.hdb
........\..\CPU.map_bb.logdb
........\..\CPU.pre_map.cdb
........\..\CPU.pre_map.hdb
........\..\CPU.rpp.qmsg
........\..\CPU.rtlv.hdb
........\..\CPU.rtlv_sg.cdb
........\..\CPU.rtlv_sg_swap.cdb
........\..\CPU.sgate.rvd
........\..\CPU.sgate_sm.rvd
........\..\CPU.sgdiff.cdb
........\..\CPU.sgdiff.hdb
........\..\CPU.sld_design_entry.sci
........\..\CPU.sld_design_entry_dsc.sci
........\..\CPU.syn_hier_info
........\..\CPU.tan.qmsg
........\..\CPU.tis_db_list.ddb
........\..\CPU.tmw_info
........\..\CPU_global_asgn_op.abo
........\..\decode_1oa.tdf
........\..\mux_hib.tdf
........\..\prev_cmp_CPU.asm.qmsg
........\..\prev_cmp_CPU.fit.qmsg
........\..\prev_cmp_CPU.map.qmsg
........\..\prev_cmp_CPU.qmsg
........\..\prev_cmp_CPU.tan.qmsg
........\..\wed.wsf
........\incremental_db\compiled_partitions\CPU.root_partition.cmp.atm
........\..............\...................\CPU.root_partition.cmp.dfp
........\..............\...................\CPU.root_partition.cmp.hdbx
........\..............\...................\CPU.root_partition.cmp.kpt
........\..............\...................\CPU.root_partition.cmp.logdb
........\..............\...................\CPU.root_partition.cmp.rcf
........\..............\...................\CPU.root_partition.map.atm
........\..............\...................\CPU.root_partition.map.dpi

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