This paper mainly discusses the design of the Verilog language, the DDS-based waveform generator. Starting from the design requirements, this paper presents the detailed design of the DDS process, including the various modules of the design ideas, schematics, Verilog language code. The general idea of frequency control word and phase control word to control the address of the ROM memory table of the sine function and the corresponding get its amplitude value, and ultimately achieve the purpose of waveform output needs.

DDS frequency synthesizer.doc

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