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[Communication-Mobile] fifo DL : 0: 一个FIFO的原代码非常有用给大家共享了下吧
Date : 2008-10-13 Size : 1.4kb User : wang
[Communication-Mobile] uart DL : 0: 这个是UART的控制器，已经跑通过，分4个模块，波特率生成、发送、接收和fifo,可供初学者参考
Date : 2008-10-13 Size : 3.68kb User : duan
[Communication-Mobile] CFifo DL : 0: cFIFO：FIFO控制类，面向运行效率优化；适合PPC,单片机编程；包含CRC校验，成帧控制。
Date : 2008-10-13 Size : 5.65kb User : Peter
[Communication-Mobile] async_fifo.v DL : 0: the verilog model of async_fifo.
Date : 2025-12-21 Size : 1kb User : nightyboy
[Communication-Mobile] fifo DL : 0: 一个FIFO的原代码非常有用给大家共享了下吧-A FIFO of the original code is very useful to the U.S. to share the next bar
Date : 2025-12-21 Size : 1kb User : wang
[Communication-Mobile] uart DL : 0: 这个是UART的控制器，已经跑通过，分4个模块，波特率生成、发送、接收和fifo,可供初学者参考-This is the UART controller, has been run through, sub-4 module, baud rate generating, sending, receiving and fifo, for beginners reference
Date : 2025-12-21 Size : 3kb User : duan
[Communication-Mobile] CFifo DL : 0: cFIFO：FIFO控制类，面向运行效率优化；适合PPC,单片机编程；包含CRC校验，成帧控制。-cFIFO: FIFO control category, operating efficiency-oriented optimization for PPC, single-chip programming contains the CRC checksum, framing control.
Date : 2025-12-21 Size : 5kb User : Peter
[Communication-Mobile] lan91c111_an96 DL : 0: 该资料为lan91c111芯片的英文原版application note，提供了使用LAN91C111进行开发所需要的软件、硬件设计、功能测试等资料。LAN91C111为SMSC公司生产的以太网控制芯片，为第三代高速以太网连接提供嵌入式解决方案。-The application note of LAN91C111.The SMSC LAN91C111 is a 32/16/8-bit Non-PCI Fast Ethernet controller that integrates on one chip a Media Access Control(MAC)Layer,a Physical Layer(PHY),8k Byte internal Dynamically Configurable TX/RX FIFO SRAM.
Date : 2025-12-21 Size : 684kb User : Charlie
[Communication-Mobile] asynchronous_fifo DL : 0: Fully asynchronous fifo for Altera devices.
Date : 2025-12-21 Size : 2kb User : kkris
[Communication-Mobile] mmtwo DL : 0: 用matlab实现 mm2 队列模型的系统仿真基于先进先出的时间连续模型-Mm2 queue system simulation model based on continuous model of the FIFO using matlab
Date : 2025-12-21 Size : 1kb User : Rebecca
[Communication-Mobile] fifo DL : 0: fifo buffer in vhdl, first in first out in vhdl, vhdl code
Date : 2025-12-21 Size : 1kb User : sgma
[Communication-Mobile] trans_and_delete DL : 0: 1/2,3/4可配置的卷积码编码，其中需要用要FIFO的IP核-1/2, 3/4 convolutional code encoder can be configured with a FIFO wherein IP core
Date : 2025-12-21 Size : 1kb User : 叶维敏
[Communication-Mobile] fifo DL : 0: fifo源码以及测试文件基于ISE14.2-fifo source and test files based on ISE14.2
Date : 2025-12-21 Size : 440kb User : mayunfeng
[Communication-Mobile] xfft_v3_2_pipe_64 DL : 0: vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband-vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband
Date : 2025-12-21 Size : 2.97mb User : xy
[Communication-Mobile] 心率 (1) DL : 0: 读取FIFO数据，装换成实际的数值，进度未加算法(Read the FIFO data and numerical into actual progress, without algorithm)
Date : 2025-12-21 Size : 4.17mb User : fc0902
[Communication-Mobile] fifo DL : 0: First In First Out for fpga
Date : 2025-12-21 Size : 28kb User : kesi