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[Com Port] simple_spi DL : 0: 一个简单的ＳＰＩ　ＩＰ核，SPI Core Specifications　可以从说明文档中找到！ The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires. FEATURES: · Compatible with Motorola’s SPI specifications · Enhanced M68HC11 Serial Peripheral Interface · 4 entries deep read FIFO · 4 entries deep write FIFO · Interrupt generation after 1, 2, 3, or 4 transferred bytes · 8 bit WISHBONE RevB.3 Classic interface · Operates from a wide range of input clock frequencies · Static synchronous design · Fully synthesizable -a simple SPI IP core, SPI Core Specifications from documentation found! The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral In terface found on Motorola's M68HC11 family of CP Us. The Serial Peripheral Interface is a serial , synchronous communication protocol that're quires a minimum of three wires. FEATURES : Compatible with Motorola's SPI specificatio ns Enhanced Serial Peripheral Interf M68HC11 ace four entries deep FIFO read four entries deep wri te FIFO Interrupt generation after 1, 2, 3, 4 or 8 bit bytes transferred RevB.3 Cl WISHBONE assic interface Operates from a wide range of i nput clock frequencies Static synchronous de sign Fully synthesizable
Date : 2008-10-13 Size : 462.01kb User : Jack
[Com Port] 485 DL : 0: 基于80C196KC微处理器的高速串行通讯、单片机将FIFO中的数据读取出来后，从串口发送出去等代码
Date : 2008-10-13 Size : 16.58kb User : didi
[Com Port] verilog_UART DL : 0: UART verilog hdl 实现-UART Verilog HDL achieve
Date : 2025-12-22 Size : 3kb User :
[Com Port] simple_spi DL : 0: 一个简单的ＳＰＩ　ＩＰ核，SPI Core Specifications　可以从说明文档中找到！ The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires. FEATURES: · Compatible with Motorola’s SPI specifications · Enhanced M68HC11 Serial Peripheral Interface · 4 entries deep read FIFO · 4 entries deep write FIFO · Interrupt generation after 1, 2, 3, or 4 transferred bytes · 8 bit WISHBONE RevB.3 Classic interface · Operates from a wide range of input clock frequencies · Static synchronous design · Fully synthesizable -a simple SPI IP core, SPI Core Specifications from documentation found! The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral In terface found on Motorola's M68HC11 family of CP Us. The Serial Peripheral Interface is a serial , synchronous communication protocol that're quires a minimum of three wires. FEATURES : Compatible with Motorola's SPI specificatio ns Enhanced Serial Peripheral Interf M68HC11 ace four entries deep FIFO read four entries deep wri te FIFO Interrupt generation after 1, 2, 3, 4 or 8 bit bytes transferred RevB.3 Cl WISHBONE assic interface Operates from a wide range of i nput clock frequencies Static synchronous de sign Fully synthesizable
Date : 2025-12-22 Size : 462kb User : Jack
[Com Port] 485 DL : 0: 基于80C196KC微处理器的高速串行通讯、单片机将FIFO中的数据读取出来后，从串口发送出去等代码-80C196KC microprocessor-based high-speed serial communications, single-chip FIFO data will be read out, etc. sent from the serial code
Date : 2025-12-22 Size : 16kb User : didi
[Com Port] serial DL : 1: Dos 串口通信例程实现了FiFO ,中断发送中断接受！-Dos serial communication routines to achieve a FiFO, interrupted send interrupt accepted!
Date : 2025-12-22 Size : 7kb User : 陈国兴
[Com Port] Uart(FIFOSend.TimeoutReceive) DL : 0: AVR mega16/mega32的UART FIFO发送.超时接收,广泛应用于工业控制.这是原创作品.-AVR mega16/mega32 send the UART FIFO. Overtime receiver is widely used in industrial control. This is the original works.
Date : 2025-12-22 Size : 24kb User : 明君
[Com Port] SCI_FIFO DL : 0: F2812 SCI FIFO中断发送和接收例程-F2812 SCI FIFO interrupt routines to send and receive
Date : 2025-12-22 Size : 2kb User : 赵伟忠
[Com Port] Serial_fifo_function DL : 0: 该文件可以实现基于44b0的串口fifo功能-The document can be achieved 44b0-based features of the serial fifo
Date : 2025-12-22 Size : 105kb User : 胡党
[Com Port] SCI_TXRXFIFO_over DL : 0: SCI串口通信程序，使用FIFO功能，定时收发-SCI serial communication, the use of FIFO function, periodically send and receive
Date : 2025-12-22 Size : 328kb User : FUYI
[Com Port] async_fifo DL : 0: 异步fifo 源程序代码欢迎大家学习用VHDL语言编写-asy fifo
Date : 2025-12-22 Size : 208kb User : chenxuhui
[Com Port] uart16550 DL : 0: uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code. -uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code.
Date : 2025-12-22 Size : 1.68mb User : CloudZhang
[Com Port] UART16550 DL : 0: UART控制器，集成FIFO，寄存器，数据位宽8位-UART controller, with FIFO, register, databus 8bits
Date : 2025-12-22 Size : 8kb User : huangluyang
[Com Port] fifo DL : 0: 基于verilog的fifo异步实现的源代码和分析。-fifo
Date : 2025-12-22 Size : 6kb User : 比尔
[Com Port] seriafifo DL : 0: LPC2124，串口FIFO，接收功能实验，触点不同，效果有区别，实验为证-LPC2124 UART FIFI example
Date : 2025-12-22 Size : 101kb User : 贾宁
[Com Port] 16550u DL : 0: Dos下使用串口实现先进先出,支持COM1-COM4- 16550 is a shareware program designed to allow the unlocking of the internal fifo buffer present in the UART chip of the same name. The program will scan all four COM ports (COM1:- COM4:) available on the PC and report the presence (if any...) of the 16550 UART. The user may optionally set the various parameters necessary to utilize this buffered mode of operation.
Date : 2025-12-22 Size : 28kb User : Seraphim
[Com Port] 51FIFO DL : 0: 51FIFO,串口缓存收发。很有借鉴意义-51FIFO, send and receive serial buffer. Useful reference
Date : 2025-12-22 Size : 1kb User : 罗伊
[Com Port] UART0_FIFO DL : 0: LPC2106的串口的FIFO仿真程序，使用ads编辑的。-LPC2106 emulator serial port of the FIFO, using ads to edit.
Date : 2025-12-22 Size : 94kb User : z
[Com Port] 51_uart_fifo51 DL : 0: 51_uart_fifo51 串口收发程序源代码环形缓冲区实现-Serial transceivers to achieve ring buffer source code
Date : 2025-12-22 Size : 47kb User : willigo
[Com Port] 10_100m_ethernet-fifo.tar DL : 0: 实现百兆以太网数据接收，可将百兆以太网数据存入FIFO中并读取。-implement 100M mac controller,and the receiver can read ethernet data,putting the data to fifo.
Date : 2025-12-22 Size : 476kb User : 李家军

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