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一个乘法器的程序,经过调试的,非常好用的,去看看.-a multiplier procedures are followed, debugging and very useful, and see.
Date : 2008-10-13 Size : 973byte User : xipengfei

signed_mult乘法器通常用于DSP设计。但由于赛灵思的FPGA架构中包含有-signed_mult multiplier is used DSP design. But Xilinx FPGA architecture contains
Date : 2008-10-13 Size : 7.36kb User : ldy

一般情况下,程序开发人员都希望自己的程序美观大方,为了达到这一个要求,想尽办法美化自己的程序,如果在界面上适当的地方添加并显示3D文字,将不失为一个好的选择,可以达到事半功倍的效果,本文针对这一问题,通过一个简单的小程序,介绍如何实现这一目标。有兴趣的读者可以稍加改动,将该方法应用到自己的程序中去。 -normal circumstances, the developers hope that their procedures emblem, in order to achieve a request, try to beautify their own procedures, if the appropriate interface and the addition of 3D display text, to be a good choice, can achieve a multiplier effect, the paper on the issue, through a simple small program on how to achieve that goal. Interested readers will be a little change, this method was applied to their programs.
Date : 2008-10-13 Size : 26.6kb User : 刘忠

解线性规划的用乘数的单纯形法-linear programming solution using the multiplier Simplex Method
Date : 2008-10-13 Size : 2.16kb User : 启东

解线性规划的用乘数的单纯形法-linear programming solution using the multiplier Simplex Method
Date : 2025-12-16 Size : 2kb User :

一个乘法器的程序,经过调试的,非常好用的,去看看.-a multiplier procedures are followed, debugging and very useful, and see.
Date : 2025-12-16 Size : 1kb User : xipengfei

signed_mult乘法器通常用于DSP设计。但由于赛灵思的FPGA架构中包含有-signed_mult multiplier is used DSP design. But Xilinx FPGA architecture contains
Date : 2025-12-16 Size : 7kb User : ldy

一般情况下,程序开发人员都希望自己的程序美观大方,为了达到这一个要求,想尽办法美化自己的程序,如果在界面上适当的地方添加并显示3D文字,将不失为一个好的选择,可以达到事半功倍的效果,本文针对这一问题,通过一个简单的小程序,介绍如何实现这一目标。有兴趣的读者可以稍加改动,将该方法应用到自己的程序中去。 -normal circumstances, the developers hope that their procedures emblem, in order to achieve a request, try to beautify their own procedures, if the appropriate interface and the addition of 3D display text, to be a good choice, can achieve a multiplier effect, the paper on the issue, through a simple small program on how to achieve that goal. Interested readers will be a little change, this method was applied to their programs.
Date : 2025-12-16 Size : 26kb User : 刘忠

1.利用FLEX10KE系列(EPM10K100EQC240-1X)的CLOCKBOOST (symbol:CLKLOCK),设计一个2倍频器,再将该倍频器2分频后输出。 对其进行时序仿真。 2.设计一个数据宽度8bit,深度是16的 同步FIFO(读写用同一时钟),具有EMPTY、FULL输出标志。 要求FIFO的读写时钟频率为20MHz, 将1-16连续写入FIFO,写满后再将其读出来(读空为止)。 仿真上述逻辑的时序,将仿真波形打印出来(与第1题放在同一个PROJECT中)。 3.设计一个数据宽度8bit,深度是16的异步FIFO(读写时钟不相同), 当读写时钟的频率分别为wrclk=40MHz、rdclk=20MHz时,仿真其逻辑波形。 -1. FLEX10KE series using (EPM10K100EQC240-1X) of CLOCKBOOST (symbol: CLKLOCK), the design of a 2 frequency multiplier, and then the multiplier 2 hours after the output frequency. Its timing simulation. 2. The design of a data width of 8bit, depth of 16 synchronous FIFO (read and write with the same clock), with EMPTY, FULL output signs. FIFO read and write requests of the clock frequency of 20MHz, the 1-16 consecutive write FIFO, written after the read (read until empty). Simulation of the above-mentioned logical timing, simulation waveforms will print out (with the No. 1 title on the same PROJECT in). 3. To design a data width of 8bit, the depth is 16 asynchronous FIFO (read and write clock is not the same), when read and write clock frequencies were wrclk = 40MHz, rdclk = 20MHz, the simulation waveform of its logic.
Date : 2025-12-16 Size : 52kb User : 李侠

超大整数相乘算法的VB实现与源代码分析,可以显示执行过程,运算速度快,有一个特点就是乘数和被乘数都必须是数字,没有涉及更高深的理论,有需要的研究一下。-Large integer multiplication algorithm with the VB source code analysis can show the process of implementation, operation speed, there is a characteristic of the multiplier and the multiplicand must be digital, there is no more deeply involved in the theory, there is a need to find out.
Date : 2025-12-16 Size : 16kb User : dfhdhy s

Baugh Wooley Multiplier
Date : 2025-12-16 Size : 1kb User : Harsha

There are 4 bit by 4 bit multiplier to give 8 bit product
Date : 2025-12-16 Size : 1kb User : abbc

基于quartus ii 9.0的99乘法器,用rom表做成的乘法器可以计算9*9的乘法,并在数码管上显示,使用时请按照自己的芯片和引脚设置。-Quartus ii 9.0 based on 99 multiplier, made by rom multiplier table can calculate the multiplication 9* 9, and in the digital control display, according to their own use when the chip and pin set.
Date : 2025-12-16 Size : 476kb User : 陈东旭

gate level implementation of 8*8 Signed baugh wooley multiplier!
Date : 2025-12-16 Size : 1kb User : Majid

此程序是用verilog语言编写的8位加法树乘法器,这种乘法器速度快,可以实现一个周期输出一个结果…-This program is written in verilog language 8-bit adder tree multiplier, the multiplier speed and the ability to achieve a cycle of output of a result ...
Date : 2025-12-16 Size : 1kb User : 风影

本程序用于计算管道流动中两相流乘子.采用分布参数法。输入条件为入口温度,流量和热流密度。-The Code is developed for calculation of two-phase multiplier in two-phase flow in tubes
Date : 2025-12-16 Size : 11kb User : fuxin

读入两个乘数,赋给x,y变量 计算两个乘数的积,赋给变量输出结果 */-Read two multiplier assigned to x, y variables calculated the product of two multipliers, the output is assigned to the variable* /
Date : 2025-12-16 Size : 7kb User : nibaichi

通过VC++建模 编写的一个具有图形 有外观的小计算器 可以进行加减乘数 小数等运算-Written by VC++ model has the appearance of a graphics calculator can add and subtract small operation like the multiplier decimal
Date : 2025-12-16 Size : 1.79mb User : zyp

计算器广泛的应用在生活方面,计算器可以进行简单的四则运算(加、减、乘、除)。键入数字时,按下相应的数字键,如果按错可用(CB)键消去一次数值,再重新输入正确的数字, 接输入数字后,按下乘号将它变为乘数,在不输入被乘数的情况下直接按(=)键,就是该数字的二次方值。根号(sqrt)键默认是开二次方根,按下(+/-)键可改变数字的正负值。-Calculator widely used in life, a simple calculator can be the four fundamental operations (addition, subtraction, multiplication, division). Type the number, press the corresponding number key, if used by mistake (CB) eliminate a key value, and then re-enter the correct number, then enter a number, press it into a multiplier multiplication, without input is directly by the case of the multiplier (=) key, that is, the value of the square of the number. Roots (sqrt) the default is to open the second root key, press the (+/-) keys to change the number of positive and negative.
Date : 2025-12-16 Size : 9kb User : dsx dsx

模拟计算机中乘法器的运行过程,用到了Booth算法-The operation of the computer simulation of the multiplier process, use of the Booth algorithm
Date : 2025-12-16 Size : 3kb User : 谢伟
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