Description: FPGA control clock and data transmission phase adjustment, can be easily carried out ADC and other high-speed interface dynamic phase adjustment;
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File list (Check if you may need any files):
01_MODEL_FIXED\My_clk.v
01_MODEL_FIXED\My_clk.xco
01_MODEL_FIXED\My_test2.v
01_MODEL_FIXED\Test_iodelay.v
01_MODEL_FIXED