Test_2_Port_RAM\Alter_LPM_2_PORT_RAM.bsf
...............\Alter_LPM_2_PORT_RAM.qip
...............\Alter_LPM_2_PORT_RAM.v
...............\Alter_LPM_2_PORT_RAM_bb.v
...............\Alter_LPM_2_PORT_RAM_inst.v
...............\Alter_LPM_2_PORT_RAM_syn.v
...............\Cyclone单口ram时序图.jpg
...............\cyclone双口ram时序图.jpg
...............\db\altsyncram_2kq1.tdf
...............\..\altsyncram_6q14.tdf
...............\..\altsyncram_6t14.tdf
...............\..\altsyncram_7f12.tdf
...............\..\altsyncram_8t14.tdf
...............\..\altsyncram_9i12.tdf
...............\..\altsyncram_ehq1.tdf
...............\..\altsyncram_ghq1.tdf
...............\..\altsyncram_gv14.tdf
...............\..\altsyncram_iv14.tdf
...............\..\altsyncram_iv22.tdf
...............\..\altsyncram_o424.tdf
...............\..\altsyncram_ojq1.tdf
...............\..\altsyncram_qjq1.tdf
...............\..\altsyncram_qv14.tdf
...............\..\cmpr_5cc.tdf
...............\..\cmpr_8cc.tdf
...............\..\cmpr_9cc.tdf
...............\..\cmpr_acc.tdf
...............\..\cmpr_bcc.tdf
...............\..\cmpr_ccc.tdf
...............\..\cntr_02j.tdf
...............\..\cntr_0ci.tdf
...............\..\cntr_45j.tdf
...............\..\cntr_4ci.tdf
...............\..\cntr_65j.tdf
...............\..\cntr_9ci.tdf
...............\..\cntr_edi.tdf
...............\..\cntr_gui.tdf
...............\..\cntr_kdi.tdf
...............\..\cntr_sbi.tdf
...............\..\cntr_ubi.tdf
...............\..\decode_1oa.tdf
...............\..\decode_9oa.tdf
...............\..\decode_rqf.tdf
...............\..\logic_util_heursitic.dat
...............\..\mux_9kb.tdf
...............\..\mux_aoc.tdf
...............\..\mux_boc.tdf
...............\..\mux_doc.tdf
...............\..\mux_elb.tdf
...............\..\mux_rlb.tdf
...............\..\prev_cmp_Test_2_Port_RAM.qmsg
...............\..\Test_2_Port_RAM.amm.cdb
...............\..\Test_2_Port_RAM.asm.qmsg
...............\..\Test_2_Port_RAM.asm.rdb
...............\..\Test_2_Port_RAM.cbx.xml
...............\..\Test_2_Port_RAM.cmp.kpt
...............\..\Test_2_Port_RAM.cmp.rdb
...............\..\Test_2_Port_RAM.cmp0.ddb
...............\..\Test_2_Port_RAM.cmp1.ddb
...............\..\Test_2_Port_RAM.cmp2.ddb
...............\..\Test_2_Port_RAM.cmp_merge.kpt
...............\..\Test_2_Port_RAM.db_info
...............\..\Test_2_Port_RAM.eda.qmsg
...............\..\Test_2_Port_RAM.fit.qmsg
...............\..\Test_2_Port_RAM.hier_info
...............\..\Test_2_Port_RAM.hif
...............\..\Test_2_Port_RAM.idb.cdb
...............\..\Test_2_Port_RAM.lpc.html
...............\..\Test_2_Port_RAM.lpc.rdb
...............\..\Test_2_Port_RAM.lpc.txt
...............\..\Test_2_Port_RAM.map.bpm
...............\..\Test_2_Port_RAM.map.cdb
...............\..\Test_2_Port_RAM.map.hdb
...............\..\Test_2_Port_RAM.map.kpt
...............\..\Test_2_Port_RAM.map.logdb
...............\..\Test_2_Port_RAM.map.qmsg
...............\..\Test_2_Port_RAM.map_bb.cdb
...............\..\Test_2_Port_RAM.map_bb.hdb
...............\..\Test_2_Port_RAM.map_bb.logdb
...............\..\Test_2_Port_RAM.pre_map.cdb
...............\..\Test_2_Port_RAM.pre_map.hdb
...............\..\Test_2_Port_RAM.rtlv.hdb
...............\..\Test_2_Port_RAM.rtlv_sg.cdb
...............\..\Test_2_Port_RAM.rtlv_sg_swap.cdb
...............\..\Test_2_Port_RAM.sgdiff.cdb
...............\..\Test_2_Port_RAM.sgdiff.hdb
...............\..\Test_2_Port_RAM.sld_design_entry.sci
...............\..\Test_2_Port_RAM.sld_design_entry_dsc.sci
...............\..\Test_2_Port_RAM.smart_action.txt
...............\..\Test_2_Port_RAM.sta.qmsg
...............\..\Test_2_Port_RAM.sta.rdb
...............\..\Test_2_Port_RAM.syn_hier_info
...............\..\Test_2_Port_RAM.tis_db_list.ddb
...............\delay_module.vhd
...............\Features_of_EP2C35F484C8.bmp
...............\greybox_tmp\cbx_args.txt
...............\incremental_db\compiled_partitions\Test_2_Port_RAM.autoh_e4eb1.map.cdb
...............\..............\...................\Test_2_Port_RAM.autoh_e4eb1.map.dpi
...............\..............\.............