Description: Simple I2C controller-- 1) No multimaster-- 2) No slave mode-- 3) No fifo's---- notes :-- Every command is acknowledged. Do not set a ne w command before previous is acknowledged.-- D is available out a clock cycle later as cmd_ack
- [i2c.tar] - This is an I2C interface VHDL source cod
- [ddsmatlab] - dds dspbuilder under the VHDL source cod
- [I2CSlave] - achieve the Verilog HDL simulation I2C S
- [fat_C] - FAT C language source code, there is no
- [tst_ds1621] - -- State machine for reading data from D
- [wishbone_i2c_master] - -- WISHBONE revB2 compiant I2C master co
- [I2Cslave] - i2c slave, this is the receiving end I2C
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