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Title: pipelined-CPU Download
 Description: verilog achieve pipelined CPU verified by simulation and downloads
 Downloaders recently: [More information of uploader 黄晓颖]
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lab28-他人
..........\ISE
..........\...\DataRAM.asy
..........\...\DataRAM.ngc
..........\...\DataRAM.sym
..........\...\DataRAM.v
..........\...\DataRAM.veo
..........\...\DataRAM.vhd
..........\...\DataRAM.vho
..........\...\DataRAM.xco
..........\...\DataRAM_flist.txt
..........\...\DataRAM_readme.txt
..........\...\DataRAM_xmdf.tcl
..........\...\mipspipelinecpu.bgn
..........\...\mipspipelinecpu.bit
..........\...\MipsPipelineCPU.bld
..........\...\MipsPipelineCPU.cel
..........\...\MipsPipelineCPU.cmd_log
..........\...\mipspipelinecpu.drc
..........\...\MipsPipelineCPU.ise
..........\...\MipsPipelineCPU.ise_ISE_Backup
..........\...\MipsPipelineCPU.lso
..........\...\MipsPipelineCPU.ncd
..........\...\MipsPipelineCPU.ngc
..........\...\MipsPipelineCPU.ngd
..........\...\MipsPipelineCPU.ngr
..........\...\MipsPipelineCPU.ntrc_log
..........\...\MipsPipelineCPU.pad
..........\...\MipsPipelineCPU.par
..........\...\MipsPipelineCPU.pcf
..........\...\MipsPipelineCPU.prj
..........\...\MipsPipelineCPU.restore
..........\...\MipsPipelineCPU.stx
..........\...\MipsPipelineCPU.syr
..........\...\mipspipelinecpu.twr
..........\...\mipspipelinecpu.twx
..........\...\MipsPipelineCPU.ucf
..........\...\MipsPipelineCPU.unroutes
..........\...\MipsPipelineCPU.ut
..........\...\MipsPipelineCPU.xpi
..........\...\MipsPipelineCPU.xst
..........\...\MipsPipelineCPU_guide.ncd
..........\...\MipsPipelineCPU_map.map
..........\...\MipsPipelineCPU_map.mrp
..........\...\MipsPipelineCPU_map.ncd
..........\...\MipsPipelineCPU_map.ngm
..........\...\MipsPipelineCPU_pad.csv
..........\...\MipsPipelineCPU_pad.txt
..........\...\MipsPipelineCPU_prev_built.ngd
..........\...\MipsPipelineCPU_summary.html
..........\...\MipsPipelineCPU_summary.xml
..........\...\MipsPipelineCPU_usage.xml
..........\...\templates
..........\...\.........\coregen.xml
..........\...\tmp
..........\...\...\_cg
..........\...\transcript
..........\...\xst
..........\...\...\dump.xst
..........\...\...\........\MipsPipelineCPU.prj
..........\...\...\........\...................\ngx
..........\...\...\........\...................\...\notopt
..........\...\...\........\...................\...\opt
..........\...\...\........\...................\ntrc.scr
..........\...\...\projnav.tmp
..........\...\...\work
..........\...\...\....\hdllib.ref
..........\...\...\....\vlg0E
..........\...\...\....\.....\adder__32bits.bin
..........\...\...\....\vlg1E
..........\...\...\....\.....\_data_r_a_m.bin
..........\...\...\....\vlg1F
..........\...\...\....\.....\_d___f_f.bin
..........\...\...\....\vlg27
..........\...\...\....\.....\mux__2to1.bin
..........\...\...\....\vlg2A
..........\...\...\....\.....\_a_l_u.bin
..........\...\...\....\vlg2F
..........\...\...\....\.....\_mips_pipeline_c_p_u.bin
..........\...\...\....\vlg30
..........\...\...\....\.....\_decode.bin
..........\...\...\....\vlg31
..........\...\...\....\.....\_e_x.bin
..........\...\...\....\.....\_i_d.bin
..........\...\...\....\vlg33
..........\...\...\....\.....\_i_f.bin
..........\...\...\....\vlg54
..........\...\...\....\.....\adder.bin
..........\...\...\....\vlg66
..........\...\...\....\.....\_d___f_f_r_e.bin
..........\...\...\....\vlg6D
..........\...\...\....\.....\_d___f_f_r.bin
..........\...\...\....\vlg73
..........\...\...\....\.....\_multi_registers.bin
..........\...\...\....\vlg7C
..........\...\...\....\.....\_instruction_r_o_m.bin
..........\...\_impact.cmd
..........\...\_impact.log
..........\...\_ngo
..........\...\....\netlist.lst
    

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