Description: VHDL-based asynchronous serial transceivers Uart receive module in the FPGA design from pc to receive serial data design the Uart send module on FPGA, the hexadecimal value of the data received from the pc plus 1 and then sent to a PC design microcontroller and FPGA interface module, the received data sent to the MCU, and displayed on the LCD
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File list (Check if you may need any files):
UART_VHDLCodes\lcd.c
..............\UART\ALL.bdf
..............\....\baud_generator.bsf
..............\....\baud_generator.vhd
..............\....\db\UART122001.asm.qmsg
..............\....\..\UART122001.cbx.xml
..............\....\..\UART122001.cmp.cdb
..............\....\..\UART122001.cmp.hdb
..............\....\..\UART122001.cmp.qrpt
..............\....\..\UART122001.cmp.rdb
..............\....\..\UART122001.cmp.tdb
..............\....\..\UART122001.cmp0.ddb
..............\....\..\UART122001.cmp2.ddb
..............\....\..\UART122001.dbp
..............\....\..\UART122001.db_info
..............\....\..\UART122001.eco.cdb
..............\....\..\UART122001.fit.qmsg
..............\....\..\UART122001.hier_info
..............\....\..\UART122001.hif
..............\....\..\UART122001.map.cdb
..............\....\..\UART122001.map.hdb
..............\....\..\UART122001.map.qmsg
..............\....\..\UART122001.pre_map.cdb
..............\....\..\UART122001.pre_map.hdb
..............\....\..\UART122001.psp
..............\....\..\UART122001.rtlv.hdb
..............\....\..\UART122001.rtlv_sg.cdb
..............\....\..\UART122001.rtlv_sg_swap.cdb
..............\....\..\UART122001.sgdiff.cdb
..............\....\..\UART122001.sgdiff.hdb
..............\....\..\UART122001.signalprobe.cdb
..............\....\..\UART122001.sld_design_entry.sci
..............\....\..\UART122001.sld_design_entry_dsc.sci
..............\....\..\UART122001.syn_hier_info
..............\....\..\UART122001.tan.qmsg
..............\....\UART122001.asm.rpt
..............\....\UART122001.cdf
..............\....\UART122001.done
..............\....\UART122001.fit.eqn
..............\....\UART122001.fit.rpt
..............\....\UART122001.fit.summary
..............\....\UART122001.flow.rpt
..............\....\UART122001.map.eqn
..............\....\UART122001.map.rpt
..............\....\UART122001.map.summary
..............\....\UART122001.pin
..............\....\UART122001.pof
..............\....\UART122001.qpf
..............\....\UART122001.qsf
..............\....\UART122001.qws
..............\....\UART122001.sof
..............\....\UART122001.tan.rpt
..............\....\UART122001.tan.summary
..............\....\UART_receiver.bsf
..............\....\UART_receiver.vhd
..............\....\UART_transmitter.bsf
..............\....\UART_transmitter.vhd
..............\....\db
..............\UART
UART_VHDLCodes
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