Description: Asynchronous FIFO, with verilog code has two modules, using the constant attention of top-level module and bottom module with quartus2 to open.
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VFIFOzipe\async_cmp.v
.........\async_fifo.v
.........\dp_ram.v
.........\rptr_empty.v
.........\wptr_full.v
VFIFOzipe
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