AMBA-Bus_Verilog_Model This source code package is

Title: AMBA-Bus_Verilog_Model

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
17kb
Update:
2012-11-26
Downloads:
2 Times
Uploaded by:
jinjinxinyi

Description: This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.

Downloaders recently: [More information of uploader jinjinxinyi]

To Search: ahb amba apb amba ahb APB bus verilo AHB APB ahb master code apb model AMBA verilog amb

[SPI_verilogHDL] - primitive code is based on Verilog HDL l
[AMBAcode(vhdl)] - realize the AMBA VHDL code
[ahb_master1] - this is a code of AMBA AHB master protoc
[apb_bridge] - arm ambm 2.0 primecell algorithm ahb con
[mmarm_EDACN] - The Verilog source code and description
[round_three_stage] - 3 stage round arbiter using verilog
[AHBtoAPB] - amba bus bridge: ahb to asb! verilog hdl
[arm9verilog] - AMBA AHB verilog Source code
[APB] - It s the verilog source code for AMBA AP
[AHB2APB_bridge] - An ahb2apb bridge with doubling algorith

File list (Check if you may need any files):

AMBA Bus_Verilog_Model\ahb_apb_bridge\rtl\ahb_apb_bridge.v
......................\.....rbiter\rtl\ahb_arbiter.v
......................\...........\...\ahb_decoder.v
......................\...........\...\ahb_default_master.v
......................\...........\...\ahb_default_slave.v
......................\...........\...\ahb_mast_mux.v
......................\...........\...\ahb_slave_mux.v
......................\....rom_slave\rtl\ahb_rom_slave.v
......................\....sram_slave\rtl\ahb_sram_slave.v
......................\defines\ahb_defines.v
......................\.......\apb_defines.v
......................\ahb_apb_bridge\rtl
......................\.....rbiter\rtl
......................\....rom_slave\rtl
......................\....sram_slave\rtl
......................\ahb_apb_bridge
......................\ahb_arbiter
......................\ahb_rom_slave
......................\ahb_sram_slave
......................\defines
AMBA Bus_Verilog_Model

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