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Title: PipelineCPU Download
 Description: This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.
 Downloaders recently: [More information of uploader huangwj644]
 To Search: quicksort verilog PIPELINE VERILOG Verilog pipeline cpu
  • [cache] - original verilog HDL achieve CACHE opera
  • [alu-div] - Quick divider with verilog HDL code is u
  • [FIFO_8_8] - FIFO FIFO queue, a cache, or a pipeline,
  • [Final_Project2] - this contains the impementation of 5 sta
  • [MIPS] - Branch prediction with the MIPS pipeline
  • [utopia] - utopia, system verilog code written in C
  • [PIPE_LINING_CPU_TEAM_24] - Quatus II compiled by the environment,
  • [CPU] - 32bit pipeline CPU
File list (Check if you may need any files): 
流水线源文件\adder.v
............\adder4.v
............\alu16.v
............\ALU_control.v
............\control_new.v
............\cpu.bdf
............\cpu.vwf
............\Data_mem.v
............\EXMEM.v
............\IDEX.v
............\IFID.v
............\ins.txt
............\Ins_mem.v
............\ins_qs.txt
............\jal.v
............\maoxian.v
............\MEMWB.v
............\mux3.v
............\Mux32_2.v
............\Mux32_4.v
............\Mux5.v
............\mux_2.v
............\PC.v
............\Registers.v
............\same.v
............\sign_extend.v
............\sign_extend2.v
............\sl2.v
............\sll2.v
............\zhuanfa.v
............\说明.txt
流水线源文件

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