Description: FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and simulation results, this procedure can be embedded directly used to do routines.
File list (Check if you may need any files):
fpga-pwm子模块\cmp_state.ini
..............\counter8.v
..............\counter8_bb.v
..............\counter8_wave0.jpg
..............\counter8_waveforms.html
..............\db\cntr_368.tdf
..............\..\cntr_697.tdf
..............\..\cntr_6c8.tdf
..............\..\cntr_am8.tdf
..............\..\fpga.asm.qmsg
..............\..\fpga.asm_labs.ddb
..............\..\fpga.cbx.xml
..............\..\fpga.cmp.cdb
..............\..\fpga.cmp.hdb
..............\..\fpga.cmp.logdb
..............\..\fpga.cmp.rdb
..............\..\fpga.cuda_io_sim_cache.ff_0.hsd
..............\..\fpga.cuda_io_sim_cache.tt_85.hsd
..............\..\fpga.dbp
..............\..\fpga.db_info
..............\..\fpga.eco.cdb
..............\..\fpga.eds_overflow
..............\..\fpga.fit.qmsg
..............\..\fpga.hier_info
..............\..\fpga.hif
..............\..\fpga.map.cdb
..............\..\fpga.map.hdb
..............\..\fpga.map.logdb
..............\..\fpga.map.qmsg
..............\..\fpga.pre_map.cdb
..............\..\fpga.pre_map.hdb
..............\..\fpga.psp
..............\..\fpga.pss
..............\..\fpga.rtlv.hdb
..............\..\fpga.rtlv_sg.cdb
..............\..\fpga.rtlv_sg_swap.cdb
..............\..\fpga.sgdiff.cdb
..............\..\fpga.sgdiff.hdb
..............\..\fpga.signalprobe.cdb
..............\..\fpga.sim.cvwf
..............\..\fpga.sim.hdb
..............\..\fpga.sim.qmsg
..............\..\fpga.sim.rdb
..............\..\fpga.sim.vwf
..............\..\fpga.sld_design_entry.sci
..............\..\fpga.sld_design_entry_dsc.sci
..............\..\fpga.sta.qmsg
..............\..\fpga.sta.rdb
..............\..\fpga.syn_hier_info
..............\..\fpga.tan.qmsg
..............\..\fpga.tiscmp.fast_1200mv_0c.ddb
..............\..\fpga.tiscmp.slow_1200mv_0c.ddb
..............\..\fpga.tiscmp.slow_1200mv_85c.ddb
..............\..\fpga.tis_db_list.ddb
..............\..\fpga_cmp.qrpt
..............\..\fpga_sim.qrpt
..............\..\prev_cmp_fpga.asm.qmsg
..............\..\prev_cmp_fpga.fit.qmsg
..............\..\prev_cmp_fpga.map.qmsg
..............\..\prev_cmp_fpga.qmsg
..............\..\prev_cmp_fpga.sim.qmsg
..............\..\prev_cmp_fpga.sta.qmsg
..............\..\prev_cmp_fpga.tan.qmsg
..............\..\wed.wsf
..............\fpga.asm.rpt
..............\fpga.cdf
..............\fpga.done
..............\fpga.dpf
..............\fpga.fit.eqn
..............\fpga.fit.rpt
..............\fpga.fit.smsg
..............\fpga.fit.summary
..............\fpga.flow.rpt
..............\fpga.map.eqn
..............\fpga.map.rpt
..............\fpga.map.summary
..............\fpga.pin
..............\fpga.pof
..............\fpga.qpf
..............\fpga.qsf
..............\fpga.qsf.bak
..............\fpga.qws
..............\fpga.sim.rpt
..............\fpga.sof
..............\fpga.sta.rpt
..............\fpga.sta.summary
..............\fpga.tan.rpt
..............\fpga.tan.summary
..............\fpga.v
..............\fpga.v.bak
..............\fpga.vwf
..............\fpgatest.v
..............\fpga_assignment_defaults.qdf
..............\rcnt8.v
..............\rcnt8_bb.v
..............\rcnt8_wave0.jpg
..............\rcnt8_waveforms.html
..............\sim.cfg
..............\sopc_builder_debug_log.txt
..............\db
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