Description: Includes not only the FPGA source code also includes a 51 SCM control source, has been achieved DDS functions, absolutely original.
- [curve] - Own a CStatic derived class, makes the s
- [mydds] - Direct Digital Synthesis (DDS), the best
- [51basedDDSsignal] - dds signals, based on 51 single-chip sys
- [AD9851_chuan] - AD9851 generate sine wave of serial prog
- [dds] - DDS-based MCU with FPGA-code, resulting
- [corna] - Using vhdl language implementation in th
- [DDS] - This is an arbitrary frequency sinusoida
- [digital_clock] - Digital clock (VHDL language) for FPGA D
- [DDS] - Based on 51 single chip AD9833 output si
File list (Check if you may need any files):
51-DDS\DDS\12232.h
......\...\1302.h
......\...\ADDA.h
......\...\DDS.c
......\...\DDS.h
......\...\DDSconfig.c
......\...\DDSconfig.h
......\...\key.bmp
......\...\Key.h
......\...\ReadRam.h
......\...\Res.h
......\...\Serial.h
......\...\STARTUP.A51
......\...\STARTUP.LST
......\...\STARTUP.OBJ
......\...\work
......\...\work.c
......\...\work.h
......\...\work.hex
......\...\work.lnp
......\...\work.LST
......\...\work.M51
......\...\work.OBJ
......\...\work.Opt
......\...\work.plg
......\...\work.Uv2
......\...\work_Opt.Bak
......\...\work_Uv2.Bak
......\...-51-FPGA\DDS-51-FPGA\DDS-2\db\add_sub_1ge.tdf
......\...........\...........\.....\..\add_sub_1me.tdf
......\...........\...........\.....\..\add_sub_3eh.tdf
......\...........\...........\.....\..\add_sub_4eh.tdf
......\...........\...........\.....\..\add_sub_4le.tdf
......\...........\...........\.....\..\add_sub_7ie.tdf
......\...........\...........\.....\..\add_sub_ahe.tdf
......\...........\...........\.....\..\add_sub_aug.tdf
......\...........\...........\.....\..\add_sub_die.tdf
......\...........\...........\.....\..\add_sub_dtg.tdf
......\...........\...........\.....\..\add_sub_ghe.tdf
......\...........\...........\.....\..\add_sub_jle.tdf
......\...........\...........\.....\..\add_sub_mke.tdf
......\...........\...........\.....\..\add_sub_rch.tdf
......\...........\...........\.....\..\add_sub_uge.tdf
......\...........\...........\.....\..\altsyncram_nk31.tdf
......\...........\...........\.....\..\altsyncram_ok31.tdf
......\...........\...........\.....\..\altsyncram_pk31.tdf
......\...........\...........\.....\..\altsyncram_qj31.tdf
......\...........\...........\.....\..\altsyncram_qk31.tdf
......\...........\...........\.....\..\altsyncram_rj31.tdf
......\...........\...........\.....\..\altsyncram_rk31.tdf
......\...........\...........\.....\..\altsyncram_sj31.tdf
......\...........\...........\.....\..\altsyncram_tj31.tdf
......\...........\...........\.....\..\altsyncram_uj31.tdf
......\...........\...........\.....\..\DDS-2.asm.qmsg
......\...........\...........\.....\..\DDS-2.cbx.xml
......\...........\...........\.....\..\DDS-2.cmp.cdb
......\...........\...........\.....\..\DDS-2.cmp.hdb
......\...........\...........\.....\..\DDS-2.cmp.logdb
......\...........\...........\.....\..\DDS-2.cmp.rdb
......\...........\...........\.....\..\DDS-2.cmp.tdb
......\...........\...........\.....\..\DDS-2.cmp0.ddb
......\...........\...........\.....\..\DDS-2.dbp
......\...........\...........\.....\..\DDS-2.db_info
......\...........\...........\.....\..\DDS-2.eco.cdb
......\...........\...........\.....\..\DDS-2.eds_overflow
......\...........\...........\.....\..\DDS-2.fit.qmsg
......\...........\...........\.....\..\DDS-2.fnsim.hdb
......\...........\...........\.....\..\DDS-2.fnsim.qmsg
......\...........\...........\.....\..\DDS-2.hier_info
......\...........\...........\.....\..\DDS-2.hif
......\...........\...........\.....\..\DDS-2.map.cdb
......\...........\...........\.....\..\DDS-2.map.hdb
......\...........\...........\.....\..\DDS-2.map.logdb
......\...........\...........\.....\..\DDS-2.map.qmsg
......\...........\...........\.....\..\DDS-2.pre_map.cdb
......\...........\...........\.....\..\DDS-2.pre_map.hdb
......\...........\...........\.....\..\DDS-2.psp
......\...........\...........\.....\..\DDS-2.pss
......\...........\...........\.....\..\DDS-2.rtlv.hdb
......\...........\...........\.....\..\DDS-2.rtlv_sg.cdb
......\...........\...........\.....\..\DDS-2.rtlv_sg_swap.cdb
......\...........\...........\.....\..\DDS-2.sgdiff.cdb
......\...........\...........\.....\..\DDS-2.sgdiff.hdb
......\...........\...........\.....\..\DDS-2.signalprobe.cdb
......\...........\...........\.....\..\DDS-2.sim.cvwf
......\...........\...........\.....\..\DDS-2.sim.hdb
......\...........\...........\.....\..\DDS-2.sim.qmsg
......\...........\...........\.....\..\DDS-2.sim.rdb
......\...........\...........\.....\..\DDS-2.sld_design_entry.sci
......\...........\...........\.....\..\DDS-2.sld_design_entry_dsc.sci
......\...........\.........
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