interleaver This is a prepared using VHDL , the us - CodeBus

Welcome！[Sign In] ！[Sign Up]！

Front-page it | Collect it | [中国-简体中文]

FAQ Fav

Location:

Embeded-SCM Develop

VHDL-FPGA-Verilog

Title: interleaver

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
1kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
chenxiaoming1985

Description: This is a prepared using VHDL interleaver, the use of interleaver enables interference by the sudden randomized into

Downloaders recently: [More information of uploader chenxiaoming1985]

To Search: Interleaver vhdl interleaver interleaver by vhdl

[cf_interleaver2] - interleaver that interleaver, which cont
[veriloginterleave2] - Interleaver in 5 source code, :-) learni
[interleave] - Data interleaver verilog HDL source file
[jzq.doc] - Mobile Communication System Designed int
[rs_forney] - algoritm Forney for rs(15_13)
[TurbojiaozhiVHDL] - something about turbo。
[4_31] - This is an interleaver/de-interleaver to
[interleaver] - This is a convolutional interleaver code
[Interleaver] - Do their own interleaver, which contains

File list (Check if you may need any files):

interleaver.v

CodeBus www.codebus.net

“CodeBus” is the largest source code store in internet!

1999-2018 CodeBus All Rights Reserved.