Verilog编写基于FPGA的示波器核心实现
...................................\oscilloscope_using_FPGA
...................................\.......................\fpge示波器
...................................\.......................\..........\c1.bsf
...................................\.......................\..........\c1.cmp
...................................\.......................\..........\c1.v
...................................\.......................\..........\c1_bb.v
...................................\.......................\..........\db
...................................\.......................\..........\..\add_sub_8tg.tdf
...................................\.......................\..........\..\add_sub_che.tdf
...................................\.......................\..........\..\add_sub_ksh.tdf
...................................\.......................\..........\..\add_sub_osh.tdf
...................................\.......................\..........\..\altsyncram_1nl2.tdf
...................................\.......................\..........\..\altsyncram_1r51.tdf
...................................\.......................\..........\..\altsyncram_3261.tdf
...................................\.......................\..........\..\altsyncram_3ln1.tdf
...................................\.......................\..........\..\altsyncram_b431.tdf
...................................\.......................\..........\..\altsyncram_fsl1.tdf
...................................\.......................\..........\..\altsyncram_mr71.tdf
...................................\.......................\..........\..\altsyncram_rr71.tdf
...................................\.......................\..........\..\altsyncram_sml2.tdf
...................................\.......................\..........\..\altsyncram_sq51.tdf
...................................\.......................\..........\..\altsyncram_t3p1.tdf
...................................\.......................\..........\..\altsyncram_t5p1.tdf
...................................\.......................\..........\..\altsyncram_usp1.tdf
...................................\.......................\..........\..\altsyncram_vpl1.tdf
...................................\.......................\..........\..\decode_ogi.tdf
...................................\.......................\..........\..\mcu_sram_test.analyze_file.qmsg
...................................\.......................\..........\..\mcu_sram_test.asm.qmsg
...................................\.......................\..........\..\mcu_sram_test.cbx.xml
...................................\.......................\..........\..\mcu_sram_test.cmp.cdb
...................................\.......................\..........\..\mcu_sram_test.cmp.hdb
...................................\.......................\..........\..\mcu_sram_test.cmp.kpt
...................................\.......................\..........\..\mcu_sram_test.cmp.logdb
...................................\.......................\..........\..\mcu_sram_test.cmp.rdb
...................................\.......................\..........\..\mcu_sram_test.cmp.tdb
...................................\.......................\..........\..\mcu_sram_test.cmp0.ddb
...................................\.......................\..........\..\mcu_sram_test.dbp
...................................\.......................\..........\..\mcu_sram_test.db_info
...................................\.......................\..........\..\mcu_sram_test.eco.cdb
...................................\.......................\..........\..\mcu_sram_test.eds_overflow
...................................\.......................\..........\..\mcu_sram_test.fit.qmsg
...................................\.......................\..........\..\mcu_sram_test.fnsim.hdb
...................................\.......................\..........\..\mcu_sram_test.fnsim.qmsg
...................................\.......................\..........\..\mcu_sram_test.hier_info
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