Description: FPGA-based digital storage oscilloscope, using VHDL achieved compression is Quartus project bag. AD sample into FPGA, after SRAM into DA in ordinary oscilloscope can display.
- [s3c2410_kaifaliucheng] - This in writing to the shift from the tr
- [DSO] - Introduced the program to achieve high-s
- [SOPC_EDA] - Contents Chapter VHDL design method of t
- [1] - With regard to the design of digital sto
- [AD-Based_on_FPGA] - VHDL language used A/D conversion proces
- [61EDA_D1070] - Oscilloscope-based VHDL design have made
- [tlc549] - The realization of digital voltage meter
- [tlc5628VHDL] - vhdl counter tlc5628
- [sram_saa1117verilog] - Image acquisition, storage, control veri
- [FPGA_AD] - Cyclone EP1C6240C8 FPGA-based interface
File list (Check if you may need any files):
EP1C3_12_5_RSV
..............\cmp_state.ini
..............\DATA
..............\....\LUT8X10.HEX
..............\....\LUT8X10.MIF
..............\db
..............\..\RESERV.db_info
..............\..\RESERV.eco.cdb
..............\dp.cmp
..............\dp.vhd
..............\dpr.cmp
..............\dpr.vhd
..............\DPRAM.VHD
..............\README
..............\......\GW48使用readme.txt
..............\RESERV.ACF
..............\RESERV.asm.rpt
..............\RESERV.CDF
..............\RESERV.done
..............\RESERV.fit.summary
..............\RESERV.flow.rpt
..............\RESERV.HIF
..............\RESERV.map.rpt
..............\RESERV.map.summary
..............\RESERV.PIN
..............\RESERV.QPF
..............\RESERV.QSF
..............\RESERV.QWS
..............\RESERV.SOF
..............\RESERV.tan.summary
..............\RESERV.VHD
..............\RESERV_assignment_defaults.qdf
..............\RRR.VHD
..............\STP1.STP
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