Description: FPGA-based phase-shifting of the DDS signal generator sine VHDL source code, compressed in the bag is done in Quartus Engineering, FPGA is used Cyclone1C3 Series
- [ddssinegeneratorcode.Rar] - described dds direct digital frequency s
- [CANsourcecode.Rar] - standard language prepared by the bus ca
- [EXPT12_10_PHAS_PLL1] - VHDL shifter DDS signal generator design
- [eda] - Application of FPGA, a sinusoidal signal
- [sina] - Sinusoidal signal generator, data, proce
- [dds_good] - The use of DDS technology waveform gener
- [dds] - FPGA-based dual phase shifter can be arb
- [VHDL-ROM4] - ROM-based design of the sine wave genera
- [dds] - dds algorithm to achieve fpga set accord
- [dds] - FPGA realization of DDS, f = 90kHZ ~ 5MH
File list (Check if you may need any files):
EP1C3_12_10_PHAS
................\ADDER10B.VHD
................\ADDER32B.VHD
................\cmp_state.ini
................\DATA
................\....\LUT10X10.HEX
................\....\LUT10X10.MIF
................\dds_vhdl.asm.rpt
................\DDS_VHDL.CDF
................\dds_vhdl.done
................\dds_vhdl.fit.summary
................\dds_vhdl.flow.rpt
................\dds_vhdl.map.summary
................\DDS_VHDL.PIN
................\DDS_VHDL.QPF
................\DDS_VHDL.QSF
................\DDS_VHDL.QWS
................\DDS_VHDL.SOF
................\dds_vhdl.tan.summary
................\DDS_VHDL.VHD
................\dds_vhdl_assignment_defaults.qdf
................\PLL20.VHD
................\README
................\......\GW48使用readme.txt
................\REG10B.VHD
................\REG32B.VHD
................\SIN_ROM.VHD
................\STP1.STP
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