pingpang On the ping-pong operation of data cache

Title: pingpang

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Category:
VHDL-FPGA-Verilog
Tags:
[ASM] [源码]
File Size:
163kb
Update:
2012-11-26
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Uploaded by:
jingsla

Description: On the ping-pong operation of data cache for the great usefulness of

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To Search: VHDL pingpang Pong ping pong sdram ping vhdl cache pong vhdl

[VHDLcommunication design of standard serial port ] - communication design programme of standa
[ping_pang] - This AHDL prepared a PCI Acquisition Sys
[E016_X-HDL3.2.52] - VHDL and Verilog code referrals tools, E
[SDRAM-HY57V641620] - Then the dynamic memory timing and worki
[UART] - The use of FPGA-FIFO, state machine, pin
[pingpangVHDL] - It is said VHDL code of the ping-pong ra
[pingpong] - Achieved a ping-pong operation, With the
[OK-fifotest-important_high_to_low] - Achieve pingpang operation of FIFO
[dp_ram] - Dual-port RAM design, using Verilog HDL
[Senior-Advanced-FPGA-design] - Senior Advanced FPGA design, about the l

File list (Check if you may need any files):

pingpang
........\automake.log
........\a_task.v
........\back.cmd_log
........\back.lso
........\back.ngc
........\back.ngr
........\back.prj
........\back.stx
........\back.syr
........\back.v
........\back_summary.html
........\back_vhdl.prj
........\b_task.cmd_log
........\b_task.lso
........\b_task.ngc
........\b_task.ngr
........\b_task.prj
........\b_task.stx
........\b_task.syr
........\b_task.v
........\b_task_summary.html
........\b_task_vhdl.prj
........\clk_contrl.cmd_log
........\clk_contrl.lso
........\clk_contrl.ngc
........\clk_contrl.ngr
........\clk_contrl.prj
........\clk_contrl.stx
........\clk_contrl.syr
........\clk_contrl.v
........\clk_contrl_summary.html
........\clk_contrl_vhdl.prj
........\front.cmd_log
........\front.lso
........\front.ngc
........\front.ngr
........\front.prj
........\front.stx
........\front.syr
........\front.v
........\front_summary.html
........\front_vhdl.prj
........\pingpang.cmd_log
........\pingpang.dhp
........\pingpang.ise
........\pingpang.ise_ISE_Backup
........\pingpang.lso
........\pingpang.ngc
........\pingpang.ngr
........\pingpang.prj
........\pingpang.stx
........\pingpang.syr
........\pingpang.v
........\pingpang_summary.html
........\pingpang_vhdl.prj
........\pingpang_xdb
........\............\tmp
........\prjname.lso
........\results.txt


........\test.ant
........\test.fdo
........\test.jhd
........\test.tbw
........\test.tfw
........\test.udo
........\test.xwv
........\test.xwv_bak
........\test_bencher.prj
........\transcript
........\vsim.wlf

........\work
........\....\a_task
........\....\......\verilog.asm
........\....\......\_primary.dat
........\....\......\_primary.vhd
........\....\back
........\....\....\verilog.asm
........\....\....\_primary.dat
........\....\....\_primary.vhd
........\....\b_task
........\....\......\verilog.asm
........\....\......\_primary.dat
........\....\......\_primary.vhd
........\....\clk_contrl
........\....\..........\verilog.asm
........\....\..........\_primary.dat
........\....\..........\_primary.vhd
........\....\front
........\....\.....\verilog.asm
........\....\.....\_primary.dat
........\....\.....\_primary.vhd
........\....\glbl
........\....\....\verilog.asm
........\....\....\_primary.dat
........\....\....\_primary.vhd
........\....\pingpang

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