Description: The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.
- [s_pandp_s] - prepared using VHDL and string conversio
- [pingpong] - VHDL language with the table tennis game
- [UART] - Verilog UART design examples, suitable f
- [uart] - A hardware description language based on
- [vlogger-2.1.1.tar] - In Linux, a key procedure to obtain, for
- [auk_sdsdi] - for FPGA design ,written by Verilog HDL
- [UART_spec] - a UART model with FIFO buffer, design wi
- [fifouart_latest.tar] - vhdl fifo uart core datasheet
File list (Check if you may need any files):
UART.pdf