Description: verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum modules, polarity transform and interpolation modules, forming filter
- [Quartusdssf] - Direct spread spectrum receiver designed
- [DDs] - This is my graduation project is the use
- [xinyuan] - Using MATLAB to achieve the spread spect
- [Carrier_Trace] - Including pseudo-code tracking and carri
- [ruan] - direct sequence spread spectrum transmit
- [16qam——modulation] - verilog modulation procedures 16qam prep
- [mydesign] - FPGA-based direct sequence spread spectr
- [18a] - Matched filter design, VERILOG implement
- [SpreadShaping] - Direct Sequence Spread Spectrum+ shaping
- [kuopin_vhdl] - Direct Sequence Spread Spectrum of the V
File list (Check if you may need any files):
baseband_verilog
................\accumulator.v
................\carrier_mixer.v
................\carrier_nco.v
................\code_gen2.v
................\code_nco.v
................\epoch_counter.v
................\gps_baseband.v
................\lgpl.txt
................\time_base.v
................\tracking_channel.v
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