Description: My project is on Direct Digital Synthesiser using Verilog HDL.This project is doing by me on july 2009 in summer training at NIT Kurukshetra, India.
This DDS system generate the square wave, Triangular wave,Sine wave and saw wave with different frequency. We can change the frequency using frequency selector input. Please accept this project. We use the SPARTAN 3E 500 device to implement it.
- [dds_control_sourcecode.ZIP] - AD9850 DDS chip driver
- [DigitalExperimentreport.Rar] - curriculum design and FPGA design to ach
- [jjcx] - Folder there are two documents, one is s
- [DDS] - In FPGA-based lookup table approach (LUT
- [FPGAddfs] - FPGA-Based Direct Digital Frequency Synt
- [DDS] - DDS debugging experience, VERIOLG the HD
- [signal] - VHDL language used to write the signal g
- [FIFO] - 512 × 8bid the FIFO with the project doc
- [DDS] - FPGA to control the AD9854 source file,
- [61EDA] - Analysis of a variety of video capture p
File list (Check if you may need any files):
clk_generator.v
DDS.v
piso_12.v
PROJECT REPORT1.doc
saw_wave.v
sinewave_generator.v
square_wave.v
triangular.v
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