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Title: traffic1 Download
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traffic1
........\component
........\constraint
........\coreconsole
........\designer
........\........\impl1
........\........\.....\designer.log
........\........\.....\designer_gen_ba.log
........\........\.....\designer_synth_check.log
........\........\.....\divide.ide_des
........\........\.....\main.adb
........\........\.....\main.dtf
........\........\.....\........\verify.log
........\........\.....\main.ide_des
........\........\.....\main.pdb
........\........\.....\main.pdb.depends
........\........\.....\main.tcl
........\........\.....\main_1_fp
........\........\.....\.........\$$FlashPro_FPBBALTLPT1.L$$
........\........\.....\.........\main.log
........\........\.....\.........\main.pro
........\........\.....\main_1_fp_1
........\........\.....\...........\$$FlashPro_FPBBALTLPT1.L$$
........\........\.....\...........\main.log
........\........\.....\...........\main.pro
........\........\.....\...........\projectData
........\........\.....\...........\...........\main.pdb
........\........\.....\main_ba.sdf
........\........\.....\main_ba.v
........\........\.....\main_fp
........\........\.....\.......\main.log
........\........\.....\.......\main.pro
........\........\.....\simulation
........\........\.....\..........\postlayout
........\........\.....\..........\..........\main
........\........\.....\..........\..........\....\verilog.psm
........\........\.....\..........\..........\....\_primary.dat
........\........\.....\..........\..........\....\_primary.dbs
........\........\.....\..........\..........\....\_primary.vhd
........\........\.....\..........\..........\stimulus
........\........\.....\..........\..........\........\verilog.psm
........\........\.....\..........\..........\........\_primary.dat
........\........\.....\..........\..........\........\_primary.dbs
........\........\.....\..........\..........\........\_primary.vhd
........\........\.....\..........\..........\tb_clock_minmax
........\........\.....\..........\..........\...............\verilog.psm
........\........\.....\..........\..........\...............\_primary.dat
........\........\.....\..........\..........\...............\_primary.dbs
........\........\.....\..........\..........\...............\_primary.vhd
........\........\.....\..........\..........\testbench
........\........\.....\..........\..........\.........\verilog.psm
........\........\.....\..........\..........\.........\_primary.dat
........\........\.....\..........\..........\.........\_primary.dbs
........\........\.....\..........\..........\.........\_primary.vhd
........\........\.....\..........\..........\_info
........\........\.....\..........\..........\_temp
........\........\.....\..........\..........\_vmake
........\........\.....\traffic.adb
........\........\.....\traffic.ide_des
........\........\.....\traffic.tcl
........\........\.....\yima.ide_des
........\hdl
........\...\divide.v
........\...\main.v
........\...\traffic.v
........\...\yima.v
........\phy_synthesis
........\simulation
........\..........\modelsim.ini
........\..........\modelsim.ini.sav
........\..........\modelsim.log
........\..........\postsynth
........\..........\.........\divide
........\..........\.........\......\verilog.psm
........\..........\.........\......\_primary.dat
........\..........\.........\......\_primary.dbs
........\..........\.........\......\_primary.vhd
........\..........\.........\main
........\..........\.........\....\verilog.psm
........\..........\.........\....\_primary.dat
........\..........\.........\....\_primary.dbs
........\..........\.........\....\_primary.vhd
........\..........\.........\stimulus
........\..........\.........\........\verilog.psm
........\..........\.........\........\_primary.dat
........\..........\.........\........\_primary.dbs
........\..........\.........\........\_primary.vhd
........\..........\.........\tb_clock_minmax
........\..........\.........\...............\verilog.psm
........\..........\.........\...............\_primary.dat
........\..........\.........\...............\_

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