Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode/Document Embeded-SCM Develop VHDL-FPGA-Verilog
Title: jtag0 Download
 Description: vhdl the procedures used to prepare the jtag interface procedures, which some of them did not materialize, hope someone can help perfect!
 Downloaders recently: [More information of uploader mabin21]
File list (Click to check if it's the file you need, and recomment it at the bottom):
jtag0
.....\0jtag0.mgf
.....\1jtag0.mgf
.....\2jtag0.mgf
.....\3jtag0.mgf
.....\bde.set
.....\compilation.order
.....\compile
.....\.......\contents.lib~
.....\.......\jtag.bdeid
.....\.......\jtag.vhd
.....\.......\jtag0.cmd
.....\.......\jtag0.epr
.....\.......\jtag0.erf
.....\.......\jtag0.top
.....\.......\jtagok.vhd
.....\.......\sources.sth
.....\compile.cfg
.....\elaboration.log
.....\fsm.set
.....\jtag0.adf
.....\jtag0.LIB
.....\jtag0.wsp
.....\log
.....\...\console.log
.....\...\jtag.htm
.....\packages.dat
.....\projlib.cfg
.....\src
.....\...\cmd_select.vhd
.....\...\cmd_shift_enable.vhd
.....\...\cmd_shift_in.vhd
.....\...\cmd_tms.vhd
.....\...\ctr_shift.vhd
.....\...\ctr_tdi.vhd
.....\...\data_input.vhd
.....\...\data_in_out_tms.vhd
.....\...\data_shift_and_out.vhd
.....\...\data_shift_enable.vhd
.....\...\dff.vhd
.....\...\jtag.bak
.....\...\jtag.bde
.....\...\rev_1
.....\...\.....\.recordref
.....\...\.....\cmd_select.edf
.....\...\.....\cmd_select.fse
.....\...\.....\cmd_select.ncf
.....\...\.....\cmd_select.srd
.....\...\.....\cmd_select.srm
.....\...\.....\cmd_select.srr
.....\...\.....\cmd_select.srs
.....\...\.....\cmd_select.tlg
.....\...\.....\syntmp
.....\...\.....\......\cmd_select.plg
.....\...\sel_ctr_tms.vhd
.....\...\sel_full_in_out_tms.vhd
.....\...\sel_infull_shift.vhd
.....\...\sel_out.vhd
.....\...\tdi3_ena.vhd
.....\...\zhiwei2.vhd
.....\...\zhiwei3.vhd
    

CodeBus www.codebus.net