Description: The module main is completed and the string conversion functions. System_clk which is an input parallel clock frequency, it is the serial clock serial_clk eight times. byte_data_en is a parallel data input enable signal, byte_data is a parallel data input. serial_data is converted serial data, bit_data_enable is the serial data signal.
- [VHDL_100Examples] - Beijing University Institute of ASIC des
- [s_pandp_s] - prepared using VHDL and string conversio
- [S2P_xapp194] - VHDL, verilog Series and conversion comp
- [FPGA_download_sch] - company Xilinx FPGA download circuit dia
- [p2s16_1] - Some time ago to see someone in the onli
- [080513154000] - Parallel to serial VHDL description: Bas
- [5] - String and the conversion process, from
- [alaw] - Use VHDL to achieve communication pulse
- [LCD] - LCD file contains a number of basic prin
File list (Check if you may need any files):
parell_to_serial.vhd
Download