Description: Discrete cosine transform and inverse discrete cosine transform of the HDL code and test files. Including VHDL and Verilog versions. And MEPG can use JPEG compression algorithm.
- [idct_122700] - IDCT inverse discrete cosine transform t
- [dct_p] - VHDL (hardware description language) wro
- [jpeg_encoder] - complete jpeg encoder Verilog code, DCT
- [eathnet] - Fast Ethernet MII and the VHDL source wa
- [DCTofJPEG] - verilog code written using JPEG compress
- [h264_deblock_ds592] - h264_deblock_ds592 FPGA development file
- [tuxiangbianhuan] - The lectures introduce image processing
- [Sdram_Control_4Port] - sopc sdram hard core of the Verilog sour
- [huffman] - The huffman algorithm for FPGA HDL codin
- [dct-code] - Discrete cosine transform VHDL realizati
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