sdram_hr_hw In FPGA hardware realize computer data

Title: sdram_hr_hw

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
4.98mb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
owein

Description: In FPGA hardware realize computer data through the serial port issued to FPGA, the data saved to SDRAM, and then again back to the computer serial port.

Downloaders recently: [More information of uploader owein]

To Search: sdram SDRAM VHDL VHDL sdram fpga

[sdram4m16_L2_42] - FPGA SDRAM with the operation of the spe
[ref-sdr-sdram-vhdl] - DDR controller VHDL source code. Using F
[EP2C5Q208] - Cyclone in series as the core EP2C5Q208
[LCD_test] - LCD_test mainly based on the VHDL langua
[AlteraSDR-SDRAM] - SDRAM controller provided by Altera in V
[connect20090223] - FPGA read data from the FIFO and upload
[USBandFPGAjiekou] - USB interface with the FPGA programming.
[async-receive] - Verilog communications procedures, the m
[PCIe-End-Point] - PCi express end point
[ram] - Using verilog implementation of dual-por

File list (Check if you may need any files):

sdram_hr_hw
...........\async_receiver.v
...........\async_transmitter.v
...........\db
...........\..\altsyncram_2hq1.tdf
...........\..\altsyncram_4hq1.tdf
...........\..\altsyncram_87p3.tdf
...........\..\altsyncram_kgq1.tdf
...........\..\altsyncram_m1p3.tdf
...........\..\altsyncram_m7p3.tdf
...........\..\altsyncram_o7p3.tdf
...........\..\altsyncram_q4p3.tdf
...........\..\cntr_02j.tdf
...........\..\cntr_0ci.tdf
...........\..\cntr_48j.tdf
...........\..\cntr_4ci.tdf
...........\..\cntr_bai.tdf
...........\..\cntr_gui.tdf
...........\..\cntr_m4j.tdf
...........\..\cntr_qbi.tdf
...........\..\cntr_sbi.tdf
...........\..\cntr_tbi.tdf
...........\..\cntr_u4j.tdf
...........\..\decode_aoi.tdf
...........\..\decode_opa.tdf
...........\..\decode_rqf.tdf
...........\..\mux_7oc.tdf
...........\..\mux_9oc.tdf
...........\..\mux_aoc.tdf
...........\..\mux_coc.tdf
...........\..\mux_llb.tdf
...........\..\prev_cmp_SDRAM_HR_HW.asm.qmsg
...........\..\prev_cmp_SDRAM_HR_HW.fit.qmsg
...........\..\prev_cmp_SDRAM_HR_HW.map.qmsg
...........\..\prev_cmp_SDRAM_HR_HW.merge.qmsg
...........\..\prev_cmp_SDRAM_HR_HW.qmsg
...........\..\prev_cmp_SDRAM_HR_HW.tan.qmsg
...........\..\SDRAM_HR_HW.asm.qmsg
...........\..\SDRAM_HR_HW.asm_labs.ddb
...........\..\SDRAM_HR_HW.autos_3e92b2e5d298f5cf757a393f7655ccd81.cmp.atm
...........\..\SDRAM_HR_HW.autos_3e92b2e5d298f5cf757a393f7655ccd81.cmp.dfp
...........\..\SDRAM_HR_HW.autos_3e92b2e5d298f5cf757a393f7655ccd81.cmp.hdbx
...........\..\SDRAM_HR_HW.autos_3e92b2e5d298f5cf757a393f7655ccd81.cmp.logdb
...........\..\SDRAM_HR_HW.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.atm
...........\..\SDRAM_HR_HW.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.hdbx
...........\..\SDRAM_HR_HW.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.kpt
...........\..\SDRAM_HR_HW.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.logdb
...........\..\SDRAM_HR_HW.cbx.xml
...........\..\SDRAM_HR_HW.cmp.bpm
...........\..\SDRAM_HR_HW.cmp.cdb
...........\..\SDRAM_HR_HW.cmp.ecobp
...........\..\SDRAM_HR_HW.cmp.hdb
...........\..\SDRAM_HR_HW.cmp.kpt
...........\..\SDRAM_HR_HW.cmp.logdb
...........\..\SDRAM_HR_HW.cmp.rdb
...........\..\SDRAM_HR_HW.cmp.tdb
...........\..\SDRAM_HR_HW.cmp0.ddb
...........\..\SDRAM_HR_HW.cmp2.ddb
...........\..\SDRAM_HR_HW.cmp_merge.kpt
...........\..\SDRAM_HR_HW.db_info
...........\..\SDRAM_HR_HW.eco.cdb
...........\..\SDRAM_HR_HW.fit.qmsg
...........\..\SDRAM_HR_HW.hier_info
...........\..\SDRAM_HR_HW.hif
...........\..\SDRAM_HR_HW.map.bpm
...........\..\SDRAM_HR_HW.map.cdb
...........\..\SDRAM_HR_HW.map.ecobp
...........\..\SDRAM_HR_HW.map.hdb
...........\..\SDRAM_HR_HW.map.kpt
...........\..\SDRAM_HR_HW.map.logdb
...........\..\SDRAM_HR_HW.map.qmsg
...........\..\SDRAM_HR_HW.map.rcf
...........\..\SDRAM_HR_HW.map_bb.cdb
...........\..\SDRAM_HR_HW.map_bb.hdb
...........\..\SDRAM_HR_HW.map_bb.hdbx
...........\..\SDRAM_HR_HW.map_bb.kpt
...........\..\SDRAM_HR_HW.map_bb.logdb
...........\..\SDRAM_HR_HW.merge.qmsg
...........\..\SDRAM_HR_HW.pre_map.cdb
...........\..\SDRAM_HR_HW.pre_map.hdb
...........\..\SDRAM_HR_HW.psp
...........\..\SDRAM_HR_HW.root_partition.cmp.atm
...........\..\SDRAM_HR_HW.root_partition.cmp.cfm
...........\..\SDRAM_HR_HW.root_partition.cmp.dfp
...........\..\SDRAM_HR_HW.root_partition.cmp.hdbx
...........\..\SDRAM_HR_HW.root_partition.cmp.logdb
...........\..\SDRAM_HR_HW.root_partition.cmp.rcf
...........\..\SDRAM_HR_HW.root_partition.map.atm
...........\..\SDRAM_HR_HW.root_partition.map.hdbx
...........\..\SDRAM_HR_HW.root_partition.map.info
...........\..\SDRAM_HR_HW.root_partition.merge_hb.atm
...........\..\SDRAM_HR_HW.rtlv.hdb
...........\..\SDRAM_HR_HW.rtlv_sg.cdb
...........\..\SDRAM_HR_HW.rtlv_sg_swap.cdb
...........\..\SDRAM_HR_HW.sgdiff.cdb
...........\..\SDRAM_HR_HW.sgdiff.hdb
...........\..\SDRAM_HR_HW.signalprobe.cdb
...........\..\SDRAM_HR_HW.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.atm
...........\..\SDRAM_HR_HW.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.dfp
...........\..\SDRAM_HR_HW.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.hdbx

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