Description: FPGA debugger, test procedures, sub-frequency. FPGA can be used for the beginner to use
To Search:
- [test_cnt] - VHDL language is only testing procedures
- [sdram_hr_hw] - In FPGA hardware realize computer data t
- [chap6] - 10 VHDL classic example of the counter i
- [VHDL38decoder] - 38 decoder VHDL language implementation,
- [uart] - uart test module with verilog langunge,i
File list (Check if you may need any files):
div
...\Block1.bdf
...\db
...\..\add_sub_5nh.tdf
...\..\div.analyze_file.qmsg
...\..\div.asm.qmsg
...\..\div.cbx.xml
...\..\div.cmp.cdb
...\..\div.cmp.hdb
...\..\div.cmp.rdb
...\..\div.cmp.tdb
...\..\div.cmp0.ddb
...\..\div.dbp
...\..\div.db_info
...\..\div.eco.cdb
...\..\div.fit.qmsg
...\..\div.hier_info
...\..\div.hif
...\..\div.map.cdb
...\..\div.map.hdb
...\..\div.map.qmsg
...\..\div.pre_map.cdb
...\..\div.pre_map.hdb
...\..\div.psp
...\..\div.pss
...\..\div.rtlv.hdb
...\..\div.rtlv_sg.cdb
...\..\div.rtlv_sg_swap.cdb
...\..\div.sgdiff.cdb
...\..\div.sgdiff.hdb
...\..\div.sld_design_entry.sci
...\..\div.sld_design_entry_dsc.sci
...\..\div.syn_hier_info
...\..\div.tan.qmsg
...\div.asm.rpt
...\div.bsf
...\div.cdf
...\div.done
...\div.dpf
...\div.fit.rpt
...\div.fit.summary
...\div.flow.rpt
...\div.map.rpt
...\div.map.summary
...\div.pin
...\div.pof
...\div.qpf
...\div.qsf
...\div.qws
...\div.sof
...\div.tan.rpt
...\div.tan.summary
...\div.v
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