Description: Write their own extensions clock, an increase of the year, month day time, verilog code in spatarn3 realize.
- [VerilogDHLdigitalclock.Rar] - Verilog language used in the preparation
- [clockv] - use Verilog language prepared by the dig
- [dirital_clock_7] - verilog electronic clock module, 60Hz in
- [Song_FPGA] - This is a source of FPGA can be achieved
- [clock] - vhdl classical source code-- Clock Desig
- [aes] - C language environment AES encryption al
- [clock] - Written using Verilog HDL Digital Clock,
- [CORDIC_DDS_16bit] - dds frequency generated files, see if th
- [clock] - With electronic clock, stopwatch, alarm
- [50M] - verilog language sub-frequency module, u
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