Groundhog implements a SATA host bus adapter. This Verilog-based project creates an easy-to-use interface between a user circuit on a Xilinx FPGA and a SATA hard drive or SSD.

groundhog_v_0_2
...............\BuildProcessTemplates
...............\.....................\DefaultTemplate.11.1.xaml
...............\.....................\LabDefaultTemplate.11.xaml
...............\.....................\UpgradeTemplate.xaml
...............\GroundhogHW_13_2
...............\................\Groundhog.gise
...............\................\Groundhog.xise
...............\HWSrc
...............\.....\hba
...............\.....\...\CRC_32.v
...............\.....\...\FIFO.v
...............\.....\...\HBA.ucf
...............\.....\...\HBA.v
...............\.....\...\Link.v
...............\.....\...\Scrambler.v
...............\.....\...\SpeedNegotiation.v
...............\.....\...\Transport.v
...............\.....\...\TransportInFIFO.v
...............\.....\ipcores
...............\.....\sirc
...............\.....\....\ethernet2BlockMem.v
...............\.....\....\ethernetController.v
...............\.....\....\fifo36Wrapper.v
...............\.....\....\iobuf.v
...............\.....\....\system.v
...............\.....\....\XUPV5system.ucf
...............\.....\tm
...............\.....\..\RNG.v
...............\.....\..\SinglePortBRAM_VHDL.vhd
...............\.....\..\TestSATA.v
...............\.....\VC709-release
...............\.....\.............\doc
...............\.....\.............\...\Create_Clk150_ipcore.pdf
...............\.....\.............\...\FMC_SATA_connection.JPG
...............\.....\.............\...\GTHSata2Instantiation.pdf
...............\.....\.............\hba
...............\.....\.............\...\CRC_32.v
...............\.....\.............\...\FIFO.v
...............\.....\.............\...\HBA.v
...............\.....\.............\...\Link.v
...............\.....\.............\...\Scrambler.v
...............\.....\.............\...\SysClkRst.ucf
...............\.....\.............\...\Transport.v
...............\.....\.............\...\TransportInFIFO.v
...............\.....\.............\...\XM104SATA.ucf
...............\.....\.............\ipcores
...............\.....\.............\.......\example_design
...............\.....\.............\.......\..............\gth_sata_gtrxreset_seq.v
...............\.....\.............\.......\..............\gth_sata_gt_usrclk_source.v
...............\.....\.............\.......\..............\gth_sata_sync_block.v
...............\.....\.............\.......\gth_sata.v
...............\.....\.............\.......\gth_sata_gt.v
...............\precompiledBinaries
...............\...................\SW_Example.exe
...............\...................\system.bit
...............\SWSrc
...............\.....\cputools.cpp
...............\.....\cputools.h
...............\.....\eth_SIRC.cpp
...............\.....\eth_SIRC.h
...............\.....\eth_SIRC.rc
...............\.....\include.h
...............\.....\main.cpp
...............\.....\packet.cpp
...............\.....\packet.h
...............\.....\resource.h
...............\.....\types.h
...............\.....\util.cpp
...............\.....\util.h
...............\SW_Example
...............\..........\SW_Example.sln
...............\..........\SW_Example.vcxproj
...............\README_v0.1.pdf
...............\CHANGELOG_v0.2.pdf

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