Verilog write serial transmission and reception module,,,,,,, I write test easy to use!

OK_FIFO_2_UART\db\altsyncram_0sj1.tdf
..............\..\altsyncram_2sj1.tdf
..............\..\altsyncram_4jf1.tdf
..............\..\altsyncram_9vj1.tdf
..............\..\altsyncram_bvj1.tdf
..............\..\altsyncram_i0k1.tdf
..............\..\altsyncram_k0k1.tdf
..............\..\a_dpfifo_0431.tdf
..............\..\a_dpfifo_dv21.tdf
..............\..\a_dpfifo_ev21.tdf
..............\..\a_dpfifo_kl71.tdf
..............\..\a_dpfifo_m231.tdf
..............\..\a_dpfifo_n231.tdf
..............\..\a_dpfifo_v331.tdf
..............\..\a_fefifo_66e.tdf
..............\..\a_fefifo_76e.tdf
..............\..\cmpr_vn8.tdf
..............\..\cntr_0ob.tdf
..............\..\cntr_a5b.tdf
..............\..\cntr_b5b.tdf
..............\..\cntr_djb.tdf
..............\..\cntr_ejb.tdf
..............\..\cntr_mmb.tdf
..............\..\cntr_n57.tdf
..............\..\cntr_nmb.tdf
..............\..\cntr_pj7.tdf
..............\..\cntr_qj7.tdf
..............\..\cntr_vnb.tdf
..............\..\dpram_5111.tdf
..............\..\dpram_6111.tdf
..............\..\dpram_e211.tdf
..............\..\dpram_f211.tdf
..............\..\dpram_st01.tdf
..............\..\dpram_tt01.tdf
..............\..\logic_util_heursitic.dat
..............\..\prev_cmp_rx_tx_interface_demo.asm.qmsg
..............\..\prev_cmp_rx_tx_interface_demo.eda.qmsg
..............\..\prev_cmp_rx_tx_interface_demo.fit.qmsg
..............\..\prev_cmp_rx_tx_interface_demo.map.qmsg
..............\..\prev_cmp_rx_tx_interface_demo.qmsg
..............\..\prev_cmp_rx_tx_interface_demo.tan.qmsg
..............\..\rx_tx_interface_demo.asm.qmsg
..............\..\rx_tx_interface_demo.asm.rdb
..............\..\rx_tx_interface_demo.cbx.xml
..............\..\rx_tx_interface_demo.cmp.idb
..............\..\rx_tx_interface_demo.cmp.kpt
..............\..\rx_tx_interface_demo.cmp.rdb
..............\..\rx_tx_interface_demo.cmp2.ddb
..............\..\rx_tx_interface_demo.cmp_merge.kpt
..............\..\rx_tx_interface_demo.cuda_io_sim_cache.31um_ff_1200mv_n40c_fast.hsd
..............\..\rx_tx_interface_demo.cuda_io_sim_cache.31um_ii_1200mv_100c_slow.hsd
..............\..\rx_tx_interface_demo.cuda_io_sim_cache.31um_ii_1200mv_85c_slow.hsd
..............\..\rx_tx_interface_demo.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
..............\..\rx_tx_interface_demo.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
..............\..\rx_tx_interface_demo.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
..............\..\rx_tx_interface_demo.db_info
..............\..\rx_tx_interface_demo.eda.qmsg
..............\..\rx_tx_interface_demo.fit.qmsg
..............\..\rx_tx_interface_demo.hier_info
..............\..\rx_tx_interface_demo.hif
..............\..\rx_tx_interface_demo.ipinfo
..............\..\rx_tx_interface_demo.lpc.html
..............\..\rx_tx_interface_demo.lpc.rdb
..............\..\rx_tx_interface_demo.lpc.txt
..............\..\rx_tx_interface_demo.map.ammdb
..............\..\rx_tx_interface_demo.map.kpt
..............\..\rx_tx_interface_demo.map.qmsg
..............\..\rx_tx_interface_demo.map_bb.cdb
..............\..\rx_tx_interface_demo.map_bb.hdb
..............\..\rx_tx_interface_demo.map_bb.logdb
..............\..\rx_tx_interface_demo.pplq.rdb
..............\..\rx_tx_interface_demo.pre_map.hdb
..............\..\rx_tx_interface_demo.pti_db_list.ddb
..............\..\rx_tx_interface_demo.root_partition.map.reg_db.cdb
..............\..\rx_tx_interface_demo.routing.rdb
..............\..\rx_tx_interface_demo.rtlv.hdb
..............\..\rx_tx_interface_demo.rtlv_sg.cdb
..............\..\rx_tx_interface_demo.rtlv_sg_swap.cdb
..............\..\rx_tx_interface_demo.sgdiff.cdb
..............\..\rx_tx_interface_demo.sgdiff.hdb
..............\..\rx_tx_interface_demo.sld_design_entry.sci
..............\..\rx_tx_interface_demo.sld_design_entry_dsc.sci
..............\..\rx_tx_interface_demo.smart_action.txt
..............\..\rx_tx_interface_demo.sta.qmsg
..............\..\rx_tx_interface_demo.sta.rdb
..............\..\rx_tx_interface_demo.syn_hier_info
..............\..\rx_tx_interface_demo.tiscmp.fastest_slow_1200mv

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