Achieved using VHDL and parallel data from the Ethernet to parallel data from the HDLC framing solution to Ethernet frames. Attached detailed code instructions, easy to read. Can be ported to Altera and Xilinx areas such as chip manufacturers are doing to FPGA-based very good information network design

HDLC协议的VHDL源码\hdlc\fifo_64.vhd
..................\....\hdlc_rx.vhd
..................\....\hdlc_tx.vhd
..................\....\top.vhd
..................\使用说明请参看右侧注释====〉〉.txt
..................\hdlc
HDLC协议的VHDL源码

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．