This section is based on fusion fpga program, is verification of serial communication program

Fusion_UART
...........\component
...........\constraint
...........\..........\uart_test.pdc
...........\coreconsole
...........\designer
...........\........\impl1
...........\........\.....\designer.log
...........\........\.....\designer_genhdl.log
...........\........\.....\simulation
...........\........\.....\uart_test.adb
...........\........\.....\uart_test.dtf
...........\........\.....\.............\verify.log
...........\........\.....\uart_test.ide_des
...........\........\.....\uart_test.pdb
...........\........\.....\uart_test.pdb.depends
...........\........\.....\uart_test.stp
...........\........\.....\uart_test.tcl
...........\........\.....\uart_test_ba.sdf
...........\........\.....\uart_test_ba.v
...........\hdl
...........\...\hdlsynchk.tcl
...........\...\rec.v
...........\...\send.v
...........\...\uart_test.v
...........\phy_synthesis
...........\simulation
...........\..........\meminit.dat
...........\..........\modelsim.ini
...........\smartgen
...........\........\smartgen.aws
...........\stimulus
...........\........\BtimErrors.log
...........\........\files_to_build.txt
...........\........\hdlsynchk.tcl
...........\........\uart_test.dsk
...........\........\uart_test.hpj
...........\........\uart_test.v
...........\........\uart_test_tbench.bk
...........\........\uart_test_tbench.btim
...........\........\uart_test_tbench.v
...........\........\waveperl.log
...........\synthesis
...........\.........\backup
...........\.........\run_options.txt
...........\.........\stdout.log
...........\.........\synthesis_identify
...........\.........\..................\syntmp
...........\.........\..................\......\identify.msg
...........\.........\..................\......\uart_test.msg
...........\.........\..................\......\uart_test_flink.htm
...........\.........\..................\uart_test.srs
...........\.........\..................\uart_test.tlg
...........\.........\syntmp
...........\.........\......\sap.log
...........\.........\......\uart_test.msg
...........\.........\......\uart_test.plg
...........\.........\......\uart_test_flink.htm
...........\.........\......\uart_test_srr.htm
...........\.........\......\uart_test_toc.htm
...........\.........\traplog.tlg
...........\.........\uart_test.areasrr
...........\.........\uart_test.edn
...........\.........\uart_test.fse
...........\.........\uart_test.htm
...........\.........\uart_test.map
...........\.........\uart_test.sap
...........\.........\uart_test.sdf
...........\.........\uart_test.srd
...........\.........\uart_test.srm
...........\.........\uart_test.srr
...........\.........\uart_test.srs
...........\.........\uart_test.tlg
...........\.........\uart_test_drc.rpt
...........\.........\uart_test_sdc.sdc
...........\.........\uart_test_syn.prj
...........\uart.prj
...........\viewdraw
...........\........\sch
...........\........\sym
...........\........\vf
...........\........\..\project.lst
...........\........\viewdraw.ini
...........\........\wir

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