I have written of the FPGA asynchronous serial communication module (UART), based on QuartusII the environment, verilog language, including simulation and all the procedures and instructions, validate through, with good stability and reference value!

UART\UART.qpf
....\UART.qsf
....\db\wed.wsf
....\..\UART.db_info
....\..\UART.cmp.rdb
....\..\UART.asm.qmsg
....\..\UART.cmp.ecobp
....\..\prev_cmp_UART.map.qmsg
....\..\UART.lpc.txt
....\..\UART.tan.qmsg
....\..\mux_5oc.tdf
....\..\UART.cbx.xml
....\..\UART.fit.qmsg
....\..\prev_cmp_UART.qmsg
....\..\UART.rtlv.hdb
....\..\UART.sim.qmsg
....\..\UART.eco.cdb
....\..\UART.sim_ori.vwf
....\..\prev_cmp_UART.sim.qmsg
....\..\mux_cqc.tdf
....\..\UART.eds_overflow
....\..\UART.sld_design_entry.sci
....\..\prev_cmp_UART.fit.qmsg
....\..\UART.simfam
....\..\prev_cmp_UART.asm.qmsg
....\..\prev_cmp_UART.tan.qmsg
....\..\UART.map.qmsg
....\..\UART.lpc.html
....\..\UART.rpp.qmsg
....\..\UART.lpc.rdb
....\..\UART.smp_dump.txt
....\..\UART.rtlv_sg.cdb
....\..\UART.pre_map.cdb
....\..\UART.map_bb.logdb
....\..\UART.sgdiff.hdb
....\..\UART.sta.qmsg
....\..\UART.cmp.logdb
....\..\UART.fnsim.qmsg
....\..\UART.rtlv_sg_swap.cdb
....\..\UART.pre_map.hdb
....\..\UART.sgdiff.cdb
....\..\prev_cmp_UART.sta.qmsg
....\..\UART.sld_design_entry_dsc.sci
....\..\UART.ae.hdb
....\..\UART.ace_cmp.bpm
....\..\UART.sim.hdb
....\..\UART.sta.rdb
....\..\UART.asm_labs.ddb
....\..\UART.map_bb.cdb
....\..\UART.sta_cmp.7_slow_1200mv_85c.tdb
....\..\UART.map.cdb
....\..\UART.sim.rdb
....\..\UART.map.logdb
....\..\UART.map.hdb
....\..\UART.map_bb.hdb
....\..\UART.ace_cmp.ecobp
....\..\UART.map.bpm
....\..\UART.sgate_sm.rvd
....\..\UART.ace_cmp.cdb
....\..\UART.hif
....\..\UART.cmp.cdb
....\..\UART.ace_cmp.hdb
....\..\UART.sgate.rvd
....\..\UART.fnsim.cdb
....\..\UART.tiscmp.slow_1200mv_85c.ddb
....\..\clk_jump.tis_db_list.ddb
....\..\UART.lfp.cdb
....\..\UART.cuda_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
....\..\UART.tmw_info
....\..\UART.cuda_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
....\..\UART.tis_db_list.ddb
....\..\UART.cmp.hdb
....\..\UART.cmp.bpm
....\..\UART.tiscmp.slow_1200mv_0c.ddb
....\..\UART.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
....\..\UART.tiscmp.fast_1200mv_0c.ddb
....\..\UART.hier_info
....\..\UART.fnsim.hdb
....\..\UART.syn_hier_info
....\..\UART.map.ecobp
....\..\UART.map.kpt
....\..\UART.cmp_merge.kpt
....\..\UART_global_asgn_op.abo
....\..\UART.cmp.kpt
....\baud.v
....\UART.sim.rpt
....\receiver.v.bak
....\UART.map.summary
....\incremental_db\compiled_partitions\UART.root_partition.map.kpt
....\..............\...................\UART.root_partition.map.atm
....\..............\...................\UART.root_partition.map.hdbx
....\..............\...................\UART.root_partition.cmp.rcf
....\..............\...................\UART.root_partition.cmp.hdbx
....\..............\...................\UART.root_partition.cmp.atm
....\..............\...................\UART.root_partition.cmp.logdb
....\..............\...................\UART.root_partition.cmp.kpt
....\..............\...................\UART.root_partition.map.dpi
....\..............\...................\UART.root_partition.cmp.dfp
....\..............\README
....\receiver.v

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