VHDL-FPGA-Verilog List Page 894

VHDL-FPGA-Verilog list

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Mold-sixty-counter Downloaded：1: FPGA-based design mold sixty counter. Runs on xilinx.
Date : 2025-09-14 Size : 4kb User :
fenping_VHDL Downloaded：0: This a slightly altered any data inside divider can be divided by (VHDL written)
Date : 2025-09-14 Size : 1kb User : 李智
VGA Downloaded：0: This is a FPGA for VGA control procedures have been validated
Date : 2025-09-14 Size : 1kb User : 李智
cordic_0_2pi Downloaded：0: This the CORDIC algorithm is a 16-bit Q14 format operation range is 0 ~ 2pi, has been verified in quartus.
Date : 2025-09-14 Size : 34kb User : 李智
Altium-designer-yuan_jian_ku Downloaded：0: altium deginer component library and package libraries
Date : 2025-09-14 Size : 16.52mb User : name
KeyToLED Downloaded：0: in the program ,wo use the key to control the led ,so wo are familiar with the FPGA Program.
Date : 2025-09-14 Size : 311kb User : 于博
FIR_lowpass Downloaded：0: FIR low-pass filtering function can achieve low frequency filtering, to good effect
Date : 2025-09-14 Size : 1kb User : 李佩青
PCI9054 Downloaded：0: PCI bus FPGA chip PCI9054 local bus control logic. Hardware architecture PCI9054+ dual-port RAM+ FPGA. Use USERo clear interrupts. The logic to apply in the project.
Date : 2025-09-14 Size : 1kb User : 61408520
SDRAMping-pong-memory-structure Downloaded：0: Dual-port RAM, ping-pong memory structure (chip model CY7C09279) applications for the FPGA to the dual-port RAM write data continuously, PCI bus read data from RAM. [Debugging has verified]
Date : 2025-09-14 Size : 1kb User : 61408520
AD9957-SPI Downloaded：1: The AD9957 contains SPI configuration program, the output is mono. Currently, the program gives only three registers configuration, if necessary, a simple reading program, you can modify the program, the program for the
Date : 2025-09-14 Size : 733kb User : 61408520
matongbu Downloaded：0: Demodulating the modulated signal, extracts the symbol clock from the synchronizing signal demodulated in order to obtain the best sampling time judgment. This program uses a lead- lag synchronization method, counter clo
Date : 2025-09-14 Size : 1kb User : 61408520
HC-SR04 Downloaded：0: HC-SR04 Ultrasonic Ranging Verilog drivers, including the driver code and test procedures, which the driver sustained high output is echoed the length of time, in us, the measurement accuracy up to 0.17mm, the program im
Date : 2025-09-14 Size : 2kb User : 郭雄

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