VHDL-FPGA-Verilog List Page 844

VHDL-FPGA-Verilog list

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PWM1khz Downloaded：0: PWM 1khz, This code allows select duty cycle using FPGA Switches.
Date : 2025-07-26 Size : 189kb User : dokuro
AdderSustract Downloaded：0: Adder-Substracter 4bits This code allows you add four bits variables or substract four bits variables. Include adder module, sbstracter module and mux2-1 module.
Date : 2025-07-26 Size : 96kb User : dokuro
Twobits-Adder Downloaded：0: Two bits Adder, this code allows add two bits variables using switches of FPGA, the result is shown in seven segments display. Include seven segments decoder module. The program was verified using BASYS 2 FPGA.
Date : 2025-07-26 Size : 50kb User : dokuro
Security-System Downloaded：0: The security system implemented monitors the state of eight doors (open or closed) and shows the state in leds when the selector indicate it. Also the number corresponding to the desired door is shown in a 7seg display.
Date : 2025-07-26 Size : 658kb User : dokuro
Frecuency-Divisor Downloaded：0: This code Use the 50 Mhz clock of BASYS 2 FPGA to generate a frecuency divisor (choose the div value using FPGA Switches). The result is shown in two leds to compare, one have a frecency fixed (with out div ) and the sec
Date : 2025-07-26 Size : 129kb User : dokuro
24 Downloaded：0: Verilog HDL code for FPGA-based 6M crystal basketball 24 seconds timer, with testbench
Date : 2025-07-26 Size : 1kb User : 单俍
ins_Decoder Downloaded：0: matrix converter
Date : 2025-07-26 Size : 4kb User : hufengge
RS485verilog Downloaded：0: This is a Verilog writing RS485 communication program, can be used, I hope we can communicate with each other,
Date : 2025-07-26 Size : 639kb User : 汪静
H891 Downloaded：0: Car ALTERA NIOS system based display system (car camera and TFT display) design source code
Date : 2025-07-26 Size : 753kb User : zhanglin
AD9548_Driver155555 Downloaded：0: ad9548 driver detailed, very comprehensive, containing the test images to share with you.
Date : 2025-07-26 Size : 824kb User : 李延刚
ones_counter Downloaded：0: 8bit counter, as shown in the file name. VHDL
Date : 2025-07-26 Size : 1.25mb User : wendy
Codes Downloaded：0: USB 2.0 using VHDL with files : main.c, drice.c and HIGH_SPEED_USB_CORE_SETUP_TRANSACTION
Date : 2025-07-26 Size : 56kb User : altenategoody

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