VHDL-FPGA-Verilog List Page 698

VHDL-FPGA-Verilog list

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UartLoop Downloaded：0: xilinx FPGA XC6LX9 serial communication program returns to send content
Date : 2025-06-28 Size : 237kb User : 书才
FX2LP-FPGA Downloaded：0: xilinx FPGA XC6LX9 and communication program CY7C68013
Date : 2025-06-28 Size : 587kb User : 书才
fir128 Downloaded：0: Discrete-Time FIR Filter, Filter length - 128, Number of Multipliers - 8, Number of States - 8.
Date : 2025-06-28 Size : 3kb User : siv
verilog_sdram Downloaded：0: I used code verilog. Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it respo
Date : 2025-06-28 Size : 28kb User : thuanbk
hash_function_sha3 Downloaded：0: The synthesis software is Xilinx ISE version 14.4. The low throughput core has been synthesized targeting a very cheap Spartan 3 (XC3S5000-4FG900). This project is licensed under the Apache License, version 2. I prefered
Date : 2025-06-28 Size : 6kb User : thuanbk
verilog-LCD1602-DS18B20 Downloaded：0: FPGA-based temperature control fan with DS18B20, LCD1602
Date : 2025-06-28 Size : 442kb User : 大哥哥
spi_verilog Downloaded：0: Development language Verilog, realize spi bus control, internal top-level file, simulation files.
Date : 2025-06-28 Size : 8kb User : 杰克
risc64 Downloaded：0: Risc 64 - Bit Verilog Code
Date : 2025-06-28 Size : 1kb User : thannasantosh
risc32_datapath Downloaded：0: Risc - 32 Bit Datapath Only
Date : 2025-06-28 Size : 1kb User : thannasantosh
ldpc_encoder_10bit Downloaded：0: LDPC Encoder 10-Bit Parity Check
Date : 2025-06-28 Size : 1kb User : thannasantosh
PS2_Final Downloaded：0: nios ii with ps2 keyboard
Date : 2025-06-28 Size : 9.09mb User : Thanh Minh Ha
DongHo Downloaded：0: design a clock using KIT DE1
Date : 2025-06-28 Size : 671kb User : Thanh Minh Ha

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