VHDL-FPGA-Verilog List Page 700

VHDL-FPGA-Verilog list

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64QAM_peng Downloaded：0: OFDM-64QAM modulation, demodulation still contain fft constellation mapping
Date : 2025-06-28 Size : 8kb User : 彭
BPSK_peng Downloaded：0: OFDM BPSK modulation and demodulation, a note, a friend in need can look
Date : 2025-06-28 Size : 3kb User : 彭
QPSK_peng Downloaded：0: OFDM QPSK modulation and demodulation, a note, a friend in need can look
Date : 2025-06-28 Size : 3kb User : 彭
BPSKQPSK16QAM64QAM Downloaded：0: OFDM modulation and demodulation, a note, a friend in need can see, personal writings
Date : 2025-06-28 Size : 2kb User : 彭
UART Downloaded：0: Verilog write a serial port code, including sending and receiving, the DE2 platform test pass.
Date : 2025-06-28 Size : 4.42mb User : lilu
dianzizhong Downloaded：0: Electronic clock, with Verilog language classroom experiments, after testing is available.
Date : 2025-06-28 Size : 11kb User : lilu
EMIF Downloaded：0: EMIF interface debugging code that USES the Verilog language, FPGA and DSP communication, testing succe
Date : 2025-06-28 Size : 131kb User : lilu
FPAG_REAL_SOURCE Downloaded：0: FPGA for advanced learner
Date : 2025-06-28 Size : 5.84mb User : liutengjun
exp5 Downloaded：0: Design using VHDL half-adder circuit, and then use component instantiation (COMPONENT) statement invokes two half adder circuit, with the structure described in the realization of a full adder.
Date : 2025-06-28 Size : 98kb User : YCZ
Four-quiz-Responder Downloaded：0: Using VHDL language quiz four Responder.Responder main function modules are: 1, for the first answer to identify and latch signal 2, scoring function. 3, digital display 4, answer limited functionality. In this design fo
Date : 2025-06-28 Size : 257kb User : YCZ
Four-binary-adder Downloaded：0: The modular design of VHDL language familiar to understand the components and packing cases call statement. Design using VHDL half-adder circuit, and then use component instantiation (COMPONENT) statement invokes two hal
Date : 2025-06-28 Size : 3.3mb User : YCZ
Count-clock-synthesis-experiments Downloaded：0: Exercise comprehensive design capabilities, including the design of a time/minutes/seconds of the clock, and you can set, clear, 12/24 hour work mode.
Date : 2025-06-28 Size : 172kb User : YCZ

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