VHDL-FPGA-Verilog List Page 703

VHDL-FPGA-Verilog list

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zhuangtaiji Downloaded：0: Convert verilog language write state machine multiple states
Date : 2025-06-28 Size : 432kb User : 龚强
half_adder Downloaded：0: VHDL code for generating half adder
Date : 2025-06-28 Size : 421kb User : mohamed
shift_right Downloaded：0: VHDL code for generaring shift register
Date : 2025-06-28 Size : 412kb User : mohamed
d_flip_en Downloaded：0: VHDL code for generating D-flip flop
Date : 2025-06-28 Size : 457kb User : mohamed
counter Downloaded：0: generating counter using VHDL
Date : 2025-06-28 Size : 431kb User : mohamed
quartus9_tst Downloaded：0: A relatively simple CPLD-based digital tube display program, suitable for beginners to learn to write using Verilog
Date : 2025-06-28 Size : 63kb User : 中国
DS18B20 Downloaded：0: Due to stringent timing requirements 18B20 generally not recommended niosii to achieve his driver. I have written based on NIOSII driver function, 50MHz frequency, can be used to ensure the temperature is accurate to 0.0
Date : 2025-06-28 Size : 2kb User : 曹操
ad9516 Downloaded：0: Configure external PLL chip AD9516 via SPI bus program on FPGA written by board-level debugging, verification is available. Program through the state machine, you will need to configure the register values 椠渀琀漀 SPI bus d
Date : 2025-06-28 Size : 3kb User : lszyx344
dac5686 Downloaded：0: Configure external DAC chip DAC5686 via SPI bus program on FPGA written by board-level debugging, verification is available. Program through the state machine, you will need to configure the register values 椠渀琀漀 SPI bus
Date : 2025-06-28 Size : 3kb User : lszyx344
ltc2183 Downloaded：0: Configure external ADC chip LTC2183 via SPI bus program on FPGA written by board-level debugging, verification is available. Program through the state machine, you will need to configure the register values 椠渀琀漀 SPI bus
Date : 2025-06-28 Size : 3kb User : lszyx344
UART Downloaded：0: Written on the FPGA to communicate via UART interface ditto-bit machine program, through board-level debugging, verification is available.
Date : 2025-06-28 Size : 6kb User : lszyx344
ADCaPLL Downloaded：0: Configure external PLL chip AD9518 and ADC9268 via SPI bus program on FPGA written by board-level debugging, verification is available. Program through the state machine, you will need to configure the register values 椠渀
Date : 2025-06-28 Size : 5kb User : lszyx344

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