VHDL-FPGA-Verilog List Page 693

VHDL-FPGA-Verilog list

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CPU Downloaded：0: Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include
Date : 2025-06-28 Size : 803kb User : wang
4.2 Downloaded：0: Manchester encoding, decoding, Verilog source code
Date : 2025-06-28 Size : 97kb User : FUDAGUO
lcd_drv Downloaded：0: LCD driver for 2-lines LCD displays with controller
Date : 2025-06-28 Size : 2kb User : Juanjo
uart_fifo_cpu_if_sv_testbench_latest.tar Downloaded：0: Serial UART with byte wide register interface for control/status, data, and baud rate.
Date : 2025-06-28 Size : 8kb User : Juanjo
uart16750_latest.tar Downloaded：0: Implements a synthesizable 16550/16750 UART core.
Date : 2025-06-28 Size : 134kb User : Juanjo
SPI_Ctrl Downloaded：0: SPI controller
Date : 2025-06-28 Size : 169kb User : flylucas
Encoder_Counter Downloaded：0: Encoder_counter DC Moter
Date : 2025-06-28 Size : 1.24mb User : Sirinapa Arjsanam
stopwatch9_02-_2---worked Downloaded：0: DE1 development board based on the production of a stopwatch with start, pause, stop, features built-in registers that can be stored in the timing display the current time
Date : 2025-06-28 Size : 913kb User : 焱斐然
ps2_keyboard Downloaded：0: PS2 keyborad keyboard scanning module can be implemented on FPGA PS2 newsletter
Date : 2025-06-28 Size : 26kb User : 焱斐然
pidviaVhdl Downloaded：0: VHDL realize PID control engine speed, built-in program instructions at a glance
Date : 2025-06-28 Size : 3kb User : 焱斐然
Calculator Downloaded：0: VHDL calculator, involving PS2 input, VGA video output, the adder, BCD transformation. You can learn more knowledge through research code
Date : 2025-06-28 Size : 1.42mb User : 焱斐然
shizhong Downloaded：0: verilog clock with hourly chime function
Date : 2025-06-28 Size : 545kb User : yuan

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