VHDL-FPGA-Verilog List Page 680

VHDL-FPGA-Verilog list

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butterfly Downloaded：0: FFT module of butterflies, need to use an adder, a subtracter, a second election selector
Date : 2025-06-27 Size : 2kb User : 徐天伟
complexMul Downloaded：0: Complex multiplier, using the ISE in the float IP core to achieve the 32 complex multiplications
Date : 2025-06-27 Size : 1kb User : 徐天伟
complexadder Downloaded：0: 32 complex adder, using the ISE in the float IP core
Date : 2025-06-27 Size : 1kb User : 徐天伟
endat Downloaded：2: endat 2.2 interface cores, sending commands to the encoder or received the encoder position values
Date : 2025-06-27 Size : 11kb User : 陈宇霆
acc Downloaded：0: This code has function to accumulate
Date : 2025-06-27 Size : 1kb User : Thinh
rrc Downloaded：0: This code implement rrc filter
Date : 2025-06-27 Size : 1kb User : Thinh
addsub Downloaded：0: This code implement add or sub between 2 number
Date : 2025-06-27 Size : 1kb User : Thinh
adder Downloaded：0: This code implement add between 2 number
Date : 2025-06-27 Size : 1kb User : Thinh
cordic_base_j Downloaded：0: This code implement a interation in cordic pipelline
Date : 2025-06-27 Size : 1kb User : Thinh
grantyz Downloaded：0: 4x phase function module using Verilog hdl language
Date : 2025-06-27 Size : 1kb User : 王驰远
divider Downloaded：0: The use of modulo 2N+1 counter, let the output clock in the X-1 (X between 0 and 2N-1) and 2N of the turning once, then can get the odd divider, but the duty ratio is not 50
Date : 2025-06-27 Size : 1kb User : houxili
shiyan Downloaded：0: FPGA design using a stopwatch, but only for simulation on
Date : 2025-06-27 Size : 457kb User : 郑龙大

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