VHDL-FPGA-Verilog List Page 677

VHDL-FPGA-Verilog list

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sequence-detector Downloaded：0: 3 bits of arbitrary binary sequence detector,simulation with Quartus 10.0+ modelsim 6.5SE，report forms
Date : 2025-06-27 Size : 88kb User : dailanfeng
Programmable-filter-design Downloaded：0: Programmable filter design,simulation with Quartus 10.0+ modelsim 6.5SE ， reports
Date : 2025-06-27 Size : 242kb User : dailanfeng
Digital-frequency-meter Downloaded：0: Digital frequency meter,simulation with Quartus 10.0+ modelsim 6.5SE ，reports。
Date : 2025-06-27 Size : 271kb User : dailanfeng
display-circuit Downloaded：0: Counter display circuit,simulation with Quartus 10.0+ modelsim 6.5SE， reports
Date : 2025-06-27 Size : 240kb User : dailanfeng
detector-(1110010) Downloaded：0: Sequence Detector (1110010) designs, simulation with Quartus 10.0+ modelsim 6.5SE ， reports
Date : 2025-06-27 Size : 160kb User : dailanfeng
VHDL-taxi Downloaded：0: Taximeter VHDL procedures, suitable for beginners.
Date : 2025-06-27 Size : 27kb User : 石磊
sencond_counter Downloaded：0: In ise14.7 development environment, using Verilog prepared stopwatch program in which the state machine implementation through dynamic digital tube display
Date : 2025-06-27 Size : 53kb User : 喻国芳
cnt Downloaded：0: In ise development environment, establish a hierarchy of top-level modules and sub-modules, and its function is to achieve a resettable class resumes proposal to suspend the stopwatch
Date : 2025-06-27 Size : 2.95mb User : 喻国芳
johnson Downloaded：0: Johnson counts
Date : 2025-06-27 Size : 228kb User : 柳攸
UART_Verilog Downloaded：0: UART Receiver module
Date : 2025-06-27 Size : 2kb User : tyb0220
FPGA_emif Downloaded：0: FPGA to emif
Date : 2025-06-27 Size : 5kb User : tyb0220
proj-ASC Downloaded：0: simple microprocessor that gives the greatest common divisor of 2 (4bit) numbers
Date : 2025-06-27 Size : 5.31mb User : octo

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