VHDL-FPGA-Verilog List Page 679

VHDL-FPGA-Verilog list

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DDS-MY-WORK-1 Downloaded：0: FPGA analog and digital signal generator DDS verilog
Date : 2025-06-27 Size : 10.19mb User : luowang
music.tar Downloaded：0: Verilog example of a program that plays some tones when connected to a speaker. Implemmented in FPGA Nexys3
Date : 2025-06-27 Size : 208kb User : yunacu
displayCounter2.tar Downloaded：0: Verilog example of a program that uses a 7 segment display (included in fpga) to display a counter 0 to 99. Implemmented in FPGA Nexys3
Date : 2025-06-27 Size : 8kb User : yunacu
inputPinsTest.tar Downloaded：0: Verilog example of a program that test the input and outputs pins FPGA by making them 1 and 0 in a specific time. Implemmented in FPGA Nexys3
Date : 2025-06-27 Size : 77kb User : yunacu
hcsr04.tar Downloaded：0: Verilog program of the interface between a FPGA and the HCSR04 arduino sensor displaying the distance measured in the 7 segment display. Implemmented in FPGA Nexys3
Date : 2025-06-27 Size : 934kb User : yunacu
LCD.tar Downloaded：0: C program of interface with a LCD display using an embedded processor (LatticeMico32) and a Nexys3 FPGA
Date : 2025-06-27 Size : 34kb User : yunacu
UsbFPGAdemo Downloaded：0: Driving USB interface chip FPGA bottom, used to transmit data to the host computer.
Date : 2025-06-27 Size : 2.09mb User : 张仰望
FPGA Downloaded：0: PGA development board used to facilitate access to information.
Date : 2025-06-27 Size : 11.25mb User : 张仰望
submit Downloaded：0: Multiplayer air fight implemented in VHDL. PS/2 and beeper supported. Two CPLD cores are required to run this demo. Final video includes.
Date : 2025-06-27 Size : 13.06mb User :
FIFO Downloaded：0: Using a written verilog write asynchronous FIFO
Date : 2025-06-27 Size : 1kb User : 丁海军
verilog Downloaded：0: VHDL programming considerations and the accumulation of experience
Date : 2025-06-27 Size : 69kb User : 丁海军
verilogAlwaysblockexplanation Downloaded：0: verilog：always block introduction
Date : 2025-06-27 Size : 913kb User : 王冲

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