VHDL-FPGA-Verilog List Page 571

VHDL-FPGA-Verilog list

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vga256 Downloaded：0: SF-EP1C development board based on a 256-color VGA display experiment, VGA display is an important part of the FPGA, this code has been studied.
Date : 2025-06-22 Size : 513kb User : 焦峰凯
FPGA_vga_char Downloaded：0: FPGA learning, VGA character display is very important, this code to display VGA characters were studied.
Date : 2025-06-22 Size : 480kb User : 焦峰凯
ex9_cof_M4K_test1 Downloaded：0: FPGA devices are usually embedded memory blocks some user-configurable, this code is based on a single M4K block RAM configuration simulation.
Date : 2025-06-22 Size : 3.87mb User : 焦峰凯
my_example Downloaded：0: Based on SOPC built CPU, LCD display with DE2-70 do with the c language written.
Date : 2025-06-22 Size : 2mb User : 天题
SOPC_LCD Downloaded：0: Based on SOPC built CPU, LCD display with DE2-70 do with the c language written.
Date : 2025-06-22 Size : 1.99mb User : 天题
6luqiangda Downloaded：0: All the buzzer, an absolute guarantee that vies to answer first module output, no back door.
Date : 2025-06-22 Size : 443kb User :
uart Downloaded：0: based on the xilinx ise and use verilog HDL language to achieve the purposes that control the uart.
Date : 2025-06-22 Size : 64kb User : 尚文东
led_111 Downloaded：0: Use xilinx s basys2 experimental class program to achieve water lights
Date : 2025-06-22 Size : 21.05mb User : 尚文东
time Downloaded：0: Using quataus, VHDL realization which has the function of the countdown counter, timer design features are timing and backward timing, can suspend count, continue to count. Alarm when backward timing counting is 0 (time
Date : 2025-06-22 Size : 1.26mb User : bella
fpganes-master Downloaded：1: fpga NES
Date : 2025-06-22 Size : 13.09mb User : 黄海岸
vga_fpga_test Downloaded：0: ise12.1 FPGA VGA
Date : 2025-06-22 Size : 127kb User : 黄海岸
risc_FPGA Downloaded：0: ISE12.1 FPGA CPU RISC
Date : 2025-06-22 Size : 1.27mb User : 黄海岸

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