VHDL-FPGA-Verilog List Page 567

VHDL-FPGA-Verilog list

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TLC1620 Downloaded：0: FPGA-based Verilog language implementation of six decimal counter
Date : 2025-06-22 Size : 221kb User :
tx_module Downloaded：0: A serial port communication, realizing the development board and the transfer of data between computers
Date : 2025-06-22 Size : 1kb User : 崔文超
ADS1278 Downloaded：1: ADS1278 8-channel ADC data collection procedures, AD sampling depth of 24bit, 16bit output reserved. Write state machine.
Date : 2025-06-22 Size : 1kb User : 郭俊媛
vga_driver Downloaded：0: Display driver works based EP3C16 of VGA. Clock 40M, pictures stored in the ROM of the FPGA, VGA display resolution is 800* 600* 60Hz, store pictures need 800* 600 (bit), due to EP3C16 the ROM is not big enough, ROM for
Date : 2025-06-22 Size : 10.73mb User : 郭俊媛
IDEA Downloaded：0: IDEA algorithm implementation
Date : 2025-06-22 Size : 2.98mb User : 曹宇
hpi Downloaded：0: 4 of C6201s through the HPI interface logic design of interconnection with CPLD, including the VHDL program
Date : 2025-06-22 Size : 3.69mb User : 郭玉东
shuzizhong Downloaded：0: VHDL language based digital clock, there are component instantiation, modify clock function Quartus II platform
Date : 2025-06-22 Size : 4.35mb User : 尜尜
SinGen Downloaded：0: Written using Verilog sine wave generation projects using ROM nuclear generation, use mif file
Date : 2025-06-22 Size : 3.91mb User : 杨玉
pingpang Downloaded：0: a Table tennis game in spartran_3A
Date : 2025-06-22 Size : 9kb User : 程伟
musicplay_v Downloaded：0: a music play program in FPGA
Date : 2025-06-22 Size : 6kb User : 程伟
Basys2_100_250General Downloaded：0: Spartan 3e basys2 Pin control file
Date : 2025-06-22 Size : 1kb User : 李超惠
spi_slave Downloaded：0: Now for the SPI slave in the FPGA. Since the SPI bus is typically much slower than the FPGA operating clock speed, we choose to over-sample the SPI bus using the FPGA clock. That makes the slave code slightly more compli
Date : 2025-06-22 Size : 1kb User : 齐宇心

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