VHDL-FPGA-Verilog List Page 569

VHDL-FPGA-Verilog list

Sort by ：

« 1 2 ... .64 .65 .66 .67 .68 569.70 .71 .72 .73 .74 ... 4310 »

ddfs Downloaded：0: IT IS THE CIRCUIT WHICH EXACTLY WORK AS SINE WAVE GENERATOR, THIS CAN BE EFFICIENTLY USED IN THE COMMUNICATIONS SYSTEMS
Date : 2025-06-22 Size : 87kb User : ajay kumar
4-2-compressor Downloaded：0: IT IS THE HYBRID COMPRESSOR WHICH WILL BE USEFUL LOW POWER SINCE THE GATE COUNT AND DELAY REQUIRED IS VERY LESS COMPARED TO THE NORMAL DESIGN
Date : 2025-06-22 Size : 1.53mb User : ajay kumar
vid_clkgen Downloaded：0: Xilinx xapp sink displayport vid clk geneator source
Date : 2025-06-22 Size : 1kb User : asdfqqqwa
submicron-technology Downloaded：0: IT IS THE TECHNOLOGY TO REDUCE THE SHORT CIRCUIT LEKAGE POWER IN CMOS TECHNOLOGY. BY THIS WE CAN AVOID THE SHORT CIRCUIT POWER
Date : 2025-06-22 Size : 7kb User : ajay kumar
image-rotation Downloaded：0: FPGA-based image processing system generator rotation, the use of image rotation system generator handler. This procedure is based on matlab run under the system generator.
Date : 2025-06-22 Size : 155kb User : wyj
SRC Downloaded：0: an implementation of Pipelined CPU in verilog
Date : 2025-06-22 Size : 7kb User : zyh
scan_led Downloaded：0: Each clock, counting time, achieve 8 scan display, turn on the digital tube display 13579BDF, can choose EDA experimental box, FPGA EP1C6Q240C8.
Date : 2025-06-22 Size : 1kb User : LP
MB Downloaded：0: Digital stopwatch design based on VHDL, FPGA experimental platform under development
Date : 2025-06-22 Size : 217kb User : 李耀
r7lite Downloaded：0: R7Lite is a PCIe Reference design based on Xilinx Kintex7 FPGA,including FPGA code ,Linux Driver and Testing A
Date : 2025-06-22 Size : 20.67mb User : yao
m_serial Downloaded：0: m sequence generation. 3 300 m-order sequence cascade, resulting in an approximate number of random numbers. Output 32 of the random numbers and the parallel clock output comprises serial output.
Date : 2025-06-22 Size : 1kb User : 汪海兵
CfgDDS_9910 Downloaded：0: dds ad9910 configuration verilog hdl program, modular design, the input data to be configured, word length, the start signal, the timing can be automatically generated, complete a configuration, the module has done hands
Date : 2025-06-22 Size : 1kb User : 汪海兵
cordic Downloaded：0: cordic code, suitable for beginners to learn and exchange
Date : 2025-06-22 Size : 1kb User : 吕攀攀

« 1 2 ... .64 .65 .66 .67 .68 569.70 .71 .72 .73 .74 ... 4310 »

Search in result