VHDL-FPGA-Verilog List Page 573

VHDL-FPGA-Verilog list

Sort by ：

« 1 2 ... .68 .69 .70 .71 .72 573.74 .75 .76 .77 .78 ... 4310 »

init_LCD Downloaded：0: Initializes Toppoly TD043MTEA1 LCD. R02: Type 1 Dot inversion, VD and HD low polarity, Latch data on falling edge, 800x480RGB R03: Software register standby, pre-charge enabled, 100 drive capacity, PWM enabled, VGL pump
Date : 2025-06-22 Size : 1kb User : Candace
qsys2014 Downloaded：0: Introduced the use of qsys, is a version of the quartus13.0 based operation, a good tutorial
Date : 2025-06-22 Size : 4.95mb User : 海风
GPS Downloaded：0: This program implements functionality GPS receiver for receiving the time information, and encoding IRIG-B time code is formed, while with the device 485 to communicate via the bus. Including schematics, SCM and CPLD pro
Date : 2025-06-22 Size : 454kb User : jiawenjing
DDS Downloaded：0: DDS-based signal generator
Date : 2025-06-22 Size : 684kb User :
sdram_basemod Downloaded：0: Sdram page can read and write capabilities, including the addition of two FIFO buffers, just a little change can join the project.
Date : 2025-06-22 Size : 4kb User :
ADC_TLC549 Downloaded：0: verilog write, use fpga comes tlc549 ADC chip voltage signal real-time acquisition and through digital display.
Date : 2025-06-22 Size : 2kb User :
rx_tx_demo Downloaded：0: Receive a small amount of a continuous string of verilog implementation, added FIFO module, can be used under slightly modified.
Date : 2025-06-22 Size : 2kb User :
sdram_singale_word Downloaded：0: Use sdram verilog-driven single-byte read and write, you can learn the most basic functions sdram, sdram reference learning program.
Date : 2025-06-22 Size : 3kb User :
saw Downloaded：0: verilog written, cleverly accomplished by counting the triangular waveform can be output directly to da.
Date : 2025-06-22 Size : 126kb User : 李俊
DDS Downloaded：0: verilog write, use the dds fpga way, you can output an arbitrary waveform signal occurs.
Date : 2025-06-22 Size : 495kb User : 李俊
test-series-10010 Downloaded：0: Used to test series 10010 program, Verilog state machine practice
Date : 2025-06-22 Size : 373kb User : 王佳
中值滤波，sobel边沿检测，腐蚀，膨胀运算，Verilog Downloaded：1: 此程序为用Verilog编写的可实现中值滤波，sobel边沿检测，腐蚀膨胀运算，算法强大。
Date : 2015-04-20 Size : 512.42kb User : mazhonglei_468@163.com

« 1 2 ... .68 .69 .70 .71 .72 573.74 .75 .76 .77 .78 ... 4310 »

Search in result