VHDL-FPGA-Verilog List Page 510

VHDL-FPGA-Verilog list

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FM_T Downloaded：0: A simple FM modulation modules for FM transmitter, using Verilog prepared, based on XILINX SPARTAN6 XC6LX9 Development
Date : 2025-06-20 Size : 1.15mb User : 郭永峰
pll Downloaded：0: An FPGA-based carrier synchronization loop design, development language Verilog, development tools ISE 14.7, FM receivers can be used, typically SDR project
Date : 2025-06-20 Size : 2.17mb User : 郭永峰
DACteste Downloaded：0: Running a test on a DAC via verilog
Date : 2025-06-20 Size : 157kb User : Alain
uart19200 Downloaded：0: uwr write_trige rxclk recv_finish clk 50MHz ref 25Mhz when bps=192
Date : 2025-06-20 Size : 2kb User : 王进才
siluqiangdaqi_FPGA_Quartus-II Downloaded：0: Achieve four answer. The circuit have a first answer signal to identify and latch function, after the moderator began to answer the reset button is pressed, and EDA training with eight digital tube display on the meter s
Date : 2025-06-20 Size : 1004kb User : 俞少迪
RTS Downloaded：0: state machine example for fpga in vhdl
Date : 2025-06-20 Size : 3.61mb User : napon
VHDL-slide-part4 Downloaded：0: a good FPGA and VHDL tutorial course slides ,part4
Date : 2025-06-20 Size : 559kb User : ss
VHDL-slide-part5 Downloaded：0: a good FPGA and VHDL tutorial course slides ,part5
Date : 2025-06-20 Size : 1.11mb User : ss
VHDL-slide-part6 Downloaded：0: a good FPGA and VHDL tutorial course slides ,part6
Date : 2025-06-20 Size : 378kb User : ss
nios2_fpga Downloaded：0: Altera nios2 proj example
Date : 2025-06-20 Size : 1.33mb User : nribeiro
timeclk Downloaded：0: Digital clock digital display minutes and seconds, every hour the buzzer 2 seconds, curriculum design, verification by
Date : 2025-06-20 Size : 646kb User : 董君
phone Downloaded：0: Phone keypad display, capable of displaying the correct key figures, figures can move right to left, it is possible to store the current phone number, with a redial function, delete, query and other functions dialed numb
Date : 2025-06-20 Size : 1.08mb User : 董君

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