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VHDL-FPGA-Verilog list
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Decoder2x4_A
Downloaded:0
The basic two pairs 4 decoder, easy to work more than four 7-segment LED scanning control
Date
: 2025-06-20
Size
: 1.3mb
User
:
chen y y
Decoder3x8
Downloaded:0
The decoder then extended to 2x4 3x8 decoder can control eight LED driving scanning circuit
Date
: 2025-06-20
Size
: 1.21mb
User
:
chen y y
Decoder7447
Downloaded:0
Basic 7-segment LED, decoding circuit can also change the associated output control codes corresponding to the associated display
Date
: 2025-06-20
Size
: 1.24mb
User
:
chen y y
sw_bit8_latch
Downloaded:0
A combination of eight key anti-bounce, plus latch circuit allows the switching action is more stable
Date
: 2025-06-20
Size
: 3.01mb
User
:
chen y y
DDS_sinwave
Downloaded:0
Simulation of DDS chip based on FPGA. Can produce more than 10M sine wave. And the waveform is not distorted.
Date
: 2025-06-20
Size
: 21kb
User
:
dalizi
FPGA_PWM
Downloaded:0
Produced by the FPGA PWM wave frequency and duty cycle can be adjusted to achieve convenient transplant.
Date
: 2025-06-20
Size
: 114kb
User
:
小松
mdio_slave_interface
Downloaded:0
Management Data Input/Output Interfaces, or MDIO, are specified in the IEEE 802.3 standard. Their primary application is to provide a Serial Management Interface (SMI) to transfer management data between an Ethernet Medi
Date
: 2025-06-20
Size
: 5kb
User
:
sherry
hdb3
Downloaded:0
encode and decode hdb3 using verilog HDL
Date
: 2025-06-20
Size
: 565kb
User
:
杨洪吉
sin_quartus9.0
Downloaded:0
Implementation of Sine wave output with different phase.
Date
: 2025-06-20
Size
: 4.04mb
User
:
俞少迪
code
Downloaded:0
convert 4 bit data to 8 bit data
Date
: 2025-06-20
Size
: 2kb
User
:
李娜
code
Downloaded:0
A, B two serial data is converted to parallel data, and then enter the adder module, add the output.
Date
: 2025-06-20
Size
: 4kb
User
:
李娜
code
Downloaded:0
7 bit voting machine, realize the voting choice results present the encoding.
Date
: 2025-06-20
Size
: 1kb
User
:
李娜
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4310
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